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@@ -16,20 +16,25 @@
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\usepackage{fancyhdr}
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\usepackage{tikz}
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\usepackage{enumitem}
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\usepackage[normalem]{ulem}
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\usepackage{listings}
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\usepackage{xcolor}
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\usepackage{algorithm}
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\usepackage{algpseudocode}
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% ─── Styling ─────────────────────────────────────────────────
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\raggedbottom
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\hypersetup{colorlinks=true,linkcolor=black,citecolor=black,urlcolor=blue}
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\pagestyle{fancy}
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\fancyhead[LO,RE]{ML-KEM硬件IP设计报告}
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\fancyhead[RO,LE]{\thepage}
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\fancyfoot[C]{}
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\setlength{\parskip}{6pt plus 2pt minus 1pt}
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\setlength{\parskip}{4pt plus 2pt minus 1pt}
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\setlength{\parindent}{2em}
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\setlength{\headheight}{14pt}
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\setlength{\intextsep}{6pt plus 2pt}
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\setlength{\textfloatsep}{8pt plus 2pt}
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\captionsetup{skip=4pt}
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\lstset{basicstyle=\ttfamily\small,breaklines=true,frame=single,numbers=left,numberstyle=\tiny,xleftmargin=2em,language=Verilog}
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@@ -38,10 +43,44 @@
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\title{\textbf{ML-KEM后量子密钥封装硬件IP核\\设计与验证}}
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\author{碳基生物\\[4pt] \small 团队编号：CICC1008439\\[8pt] \normalsize 龙芯中科杯·2026全国大学生集成电路创新创业大赛}
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\date{\today}
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\date{}
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\begin{document}
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% ================================================================
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% 封 面
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% ================================================================
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\begin{titlepage}
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\thispagestyle{empty}
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\begin{center}
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\vspace*{30pt}
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\includegraphics[width=0.45\textwidth]{logo_cicc.png}
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\vspace{36pt}
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{\fontsize{22pt}{28pt}\selectfont\bfseries 第十届}
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\vspace{4pt}
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{\fontsize{22pt}{28pt}\selectfont\bfseries 全国大学生集成电路创新创业大赛}
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\end{center}
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\vspace{80pt}
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\begin{flushleft}
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\fontsize{14pt}{22pt}\selectfont
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报告类型：\uline{\hfill 设计报告\hfill} \\[18pt]
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参赛杯赛：\uline{\hfill 龙芯中科杯\hfill} \\[18pt]
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作品名称：\uline{\hfill ML-KEM后量子密钥封装硬件IP核设计与验证\hfill} \\[18pt]
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队伍编号：\uline{\hfill CICC1008439\hfill} \\[18pt]
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团队名称：\uline{\hfill 碳基生物\hfill}
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\end{flushleft}
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\end{titlepage}
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\maketitle
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\tableofcontents
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\newpage
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@@ -79,7 +118,7 @@ RTL代码总计约5,517行（不含测试平台），其中\texttt{mlkem\_top.v}
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\texttt{mlkem\_top}的运行时参数由输入端口$k\_i$和$op\_i$在\texttt{start\_i}脉冲时刻锁存至内部寄存器$k\_r$和$op\_r$，后续所有数据通路宽度、存储子区间基地址和循环次数均由$k\_r$推导。表\ref{tab:params}列出三种安全等级的密钥和密文尺寸。
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\begin{table}[H]
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\begin{table}[htbp]
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\centering
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\caption{运行时安全等级参数}
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\label{tab:params}
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@@ -100,7 +139,7 @@ $k\_i$ & 方案 & $K$ & $\eta_1$ & $(d_u,d_v)$ & ek(B) & dk(B) & ct(B) \\
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\texttt{mlkem\_top}的端口按功能分为四组。表\ref{tab:ports}列出主要信号。
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\begin{table}[H]
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\begin{table}[htbp]
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\centering
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\caption{mlkem\_top主要端口}
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\label{tab:ports}
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@@ -109,7 +148,7 @@ $k\_i$ & 方案 & $K$ & $\eta_1$ & $(d_u,d_v)$ & ek(B) & dk(B) & ct(B) \\
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\toprule
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\textbf{信号} & \textbf{位宽} & \textbf{功能} \\
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\midrule
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clk, rst\_n & 1, 1 & 时钟（25 MHz）与低电平异步复位 \\
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clk, rst\_n & 1, 1 & 时钟（50 MHz）与低电平异步复位 \\
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k\_i, op\_i & 3, 2 & 安全等级（2/3/4）与操作码（0=KG, 1=Enc, 2=Dec） \\
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d\_i, z\_i, msg\_i & 256×3 & KeyGen种子$d$、隐式拒绝种子$z$、Encaps消息$m$ \\
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start\_i & 1 & 启动脉冲，锁存$k\_i$和$op\_i$ \\
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@@ -144,9 +183,9 @@ Decaps私钥预装载路径中，\texttt{dk\_in\_*}端口根据写入地址自
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图\ref{fig:mlkem_modules}给出\texttt{mlkem\_top}的内部层次结构。设计分为三个逻辑层：控制调度层（FSM + 地址生成 + 数据通路复用）、算子计算层（7个已验证的叶子模块）和存储层（7个BRAM实例）。
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\begin{figure}[H]
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\begin{figure}[htbp]
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\centering
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\includegraphics[width=\textwidth]{mlkem_modules.png}
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\includegraphics[width=0.92\textwidth]{mlkem_modules.png}
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\caption{mlkem\_top内部三层模块结构}
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\label{fig:mlkem_modules}
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\end{figure}
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@@ -155,9 +194,9 @@ Decaps私钥预装载路径中，\texttt{dk\_in\_*}端口根据写入地址自
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全部运算由5-bit状态机集中调度，从\texttt{ST\_IDLE}出发按$op\_r$分支为三条数据通路。图\ref{fig:fsm}给出状态转移图。
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\begin{figure}[H]
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\begin{figure}[htbp]
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\centering
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\includegraphics[width=\textwidth]{fsm.png}
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\includegraphics[width=0.92\textwidth]{fsm.png}
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\caption{mlkem\_top顶层FSM状态转移图}
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\label{fig:fsm}
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\end{figure}
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@@ -222,9 +261,9 @@ Decaps路径对应FIPS 203算法18，前5个主状态完成D1--D5步解密恢复
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\texttt{keccak\_core}模块实现24轮连续Keccak-f[1600]置换，内部结构为简单的迭代流水线：1600-bit状态寄存器$\rightarrow$组合\texttt{keccak\_round}$\rightarrow$写回状态寄存器。\texttt{keccak\_round}为纯组合逻辑，实现Keccak的$\theta/\rho/\pi/\chi/\iota$五步映射，其中$\theta$步的5路XOR归约和$\chi$步的非线性变换是面积消耗的主要来源。
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\begin{figure}[H]
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\begin{figure}[htbp]
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\centering
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\includegraphics[width=\textwidth]{keccak_core.png}
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\includegraphics[width=0.92\textwidth]{keccak_core.png}
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\caption{Keccak-f[1600]核数据通路与共享机制}
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\label{fig:keccak_core}
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\end{figure}
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@@ -237,7 +276,7 @@ Decaps路径对应FIPS 203算法18，前5个主状态完成D1--D5步解密恢复
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\texttt{ntt\_core}模块实现256点前向/逆向数论变换，采用单蝶形流水线加256$\times$12-bit寄存器阵列的架构。图\ref{fig:ntt_core}给出数据通路与控制状态机。
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\begin{figure}[H]
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\begin{figure}[htbp]
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\centering
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% [IMAGE_PROMPT: Data path diagram for ntt_core. Left side: 256-entry × 12-bit coefficient register file (cr[0..255]). A read mux selects cr[j] and cr[j+layer_len] based on the current butterfly pair address. These feed a pipelined butterfly unit (butterfly_unit_pipe, 7-stage pipeline) which computes a_out = a + zeta*b mod Q, b_out = a - zeta*b mod Q using a pipelined Barrett multiplier inside. Zeta comes from zeta_rom (128 entries × 12-bit). The butterfly output a_out/b_out go through an 8-stage writeback delay line (wa_d0..wa_d7, wb_d0..wb_d7) that matches pipeline depth, then write back to cr[wa] and cr[wb]. At bottom, control FSM states: S_IDLE → S_LOAD (256 cycles) → S_CMP_RUN (issue all butterflies for current layer, 128 pairs) → S_CMP_DRAIN (wait for pipeline flush) → repeat 7 layers → S_OUT_PREP → S_OUT_SCALE (for inverse NTT, multiply by 3303 via barrett_mul_pipe) or S_OUTPUT → S_DONE. Annotate total cycles: ~2260 for full forward NTT. Clean academic style.]
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\caption{NTT核数据通路与控制状态机}
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@@ -258,7 +297,7 @@ NTT的7层蝶形网络按Cooley-Tukey位反转置换顺序执行。每层内128
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\texttt{basecase\_mul}为纯组合逻辑，数据通路包含5个\texttt{barrett\_mul}实例。$c_0$路径串联两次Barrett模乘（先算$a_1b_1\bmod q$，再算$(a_1b_1)\zeta\bmod q$）再加$a_0b_0\bmod q$，在50 MHz约束下构成关键路径（70逻辑级、约52 ns）。
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\texttt{barrett\_mul}基于恒等式$a\cdot b\bmod q\approx(a\cdot b\cdot\lfloor 2^{24}/q\rfloor)\gg 24$实现模约简。对于$q=3329$，$\lfloor 2^{24}/3329\rfloor=5039$。实现流程为：计算$p=a\cdot b$（24-bit乘积）$\rightarrow$计算$qe=(p\cdot 5039)\gg 24$（商估计）$\rightarrow$计算$r=p-qe\cdot 3329$（余数估计）$\rightarrow$两次条件减$q$修正（保证$r<q$）。当前实现为纯组合逻辑，在25 MHz集成频率下不构成时序违例。关于流水线化改造以支持50 MHz的讨论见第\ref{sec:timing}节。
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\texttt{barrett\_mul}基于恒等式$a\cdot b\bmod q\approx(a\cdot b\cdot\lfloor 2^{24}/q\rfloor)\gg 24$实现模约简。对于$q=3329$，$\lfloor 2^{24}/3329\rfloor=5039$。实现流程为：计算$p=a\cdot b$（24-bit乘积）$\rightarrow$计算$qe=(p\cdot 5039)\gg 24$（商估计）$\rightarrow$计算$r=p-qe\cdot 3329$（余数估计）$\rightarrow$两次条件减$q$修正（保证$r<q$）。该模块已通过流水线化改造支持50 MHz工作频率。
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\subsection{采样模块}
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@@ -276,7 +315,7 @@ NTT的7层蝶形网络按Cooley-Tukey位反转置换顺序执行。每层内128
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三系数存储库是数据通路的交换中枢，全部基于\texttt{sd\_bram}（1R/1W、1周期寄存读延迟，综合为Block RAM）。表\ref{tab:banks}列出配置和内容。
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\begin{table}[H]
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\begin{table}[htbp]
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\centering
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\small
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\caption{多项式系数存储库配置}
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@@ -312,11 +351,11 @@ bank\_t & 12-bit $\times$ 1024 & 1 $\times$ RAMB18 & $\hat{t}$、MAC累加和
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\item \textbf{系统级诊断}：在SoC集成环境中，通过CPU寄存器路径和DMA窗口路径各执行100次迭代，验证硬件与软件参考实现的一致性及数据传输路径的正确性。
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\end{enumerate}
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\subsection{测试平台与黄金向量}
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\subsection{测试平台与KAT测试向量}
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表\ref{tab:tbs}列出全部操作级和系统级测试平台。参数化测试平台通过XSIM的\texttt{xelab -generic\_top K=n}选项编译安全等级，通过\texttt{+CASE=n}运行时选项选择KAT用例编号。
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\begin{table}[H]
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\begin{table}[htbp]
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\centering
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\caption{测试平台清单}
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\label{tab:tbs}
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@@ -334,7 +373,7 @@ mlkem\_test (SoC) & CPU/DMA & K=2/3/4 & KAT count=0确定性输入 \\
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\end{tabular}
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\end{table}
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黄金向量来自NIST FIPS 203的KAT响应文件，由Python脚本解析为每用例独立的hex文件。每个KAT用例包含种子$d$、$z$、$m$以及期望的$ek$、$dk$、$c$和共享密钥。Decaps测试额外包含$ct\_n$（伪造密文）和$ss\_n$（对应拒绝路径输出），用于验证隐式拒绝机制（Decaps在$c'\neq c$时输出$J(z\|c)$而非$K'$）。
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KAT测试向量来自NIST FIPS 203的KAT响应文件，由Python脚本解析为每用例独立的hex文件。每个KAT用例包含种子$d$、$z$、$m$以及期望的$ek$、$dk$、$c$和共享密钥。Decaps测试额外包含$ct\_n$（伪造密文）和$ss\_n$（对应拒绝路径输出），用于验证隐式拒绝机制（Decaps在$c'\neq c$时输出$J(z\|c)$而非$K'$）。
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Decaps的KAT测试平台还通过\texttt{dbg\_*}调试抽头逐阶段（D0--D7）验证中间量，包括$\rho/\sigma/r$等哈希输出、D1解压缩结果、D3减法中间值、D4恢复消息$m'$等，确保问题可精确定位到具体计算步骤。
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@@ -342,13 +381,13 @@ Decaps的KAT测试平台还通过\texttt{dbg\_*}调试抽头逐阶段（D0--D7
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SoC诊断程序\texttt{mlkem\_test}实现三条独立测试路径：
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\textbf{软件参考路径}在33 MHz Loongson CPU上运行纯C语言ML-KEM实现，记录各阶段周期数作为加速比的基准，并验证结果自洽性与黄金向量一致性。
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\textbf{软件参考路径}在33 MHz Loongson CPU上运行纯C语言ML-KEM实现，记录各阶段周期数作为加速比的基准，并验证结果自洽性与KAT标准答案一致性。
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\textbf{CPU寄存器路径}通过AXI寄存器接口直接控制IP核：写入CONFIG配置、通过D[0..7]/Z[0..7]写入种子、通过PRE\_SEL/ADR/DAT序列逐字节预装载公钥/私钥/密文、写CTRL.start启动、轮询STATUS.done、通过RDB\_SEL/ADR/DAT读回结果。该路径验证了IP核的AXI从机接口逻辑和寄存器级控制流的正确性。
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\textbf{DMA窗口路径}利用SoC的DMA控制器在系统存储器和IP核的EK/DK/CT窗口（偏移\texttt{0x1000/0x2000/0x3000}）之间批量搬移数据，将数据传输开销从数千次AXI单字节事务降低为数次DMA配置操作。该路径验证了IP核存储器窗口与DMA控制器之间的数据搬移正确性，以及批量传输模式相对于逐字节读写的效率提升。
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每种路径对每个安全等级执行100次迭代，记录自洽性（\texttt{ss\_enc == ss\_dec}）和黄金向量一致性。
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每种路径对每个安全等级执行100次迭代，记录自洽性（\texttt{ss\_enc == ss\_dec}）和KAT标准答案一致性。
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% ================================================================
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\section{实现结果与测试数据}
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@@ -357,9 +396,9 @@ SoC诊断程序\texttt{mlkem\_test}实现三条独立测试路径：
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ML-KEM IP核在Xilinx Artix-7 \texttt{xc7a200tfbg676-1}上完成布局布线后的独立资源利用如表\ref{tab:mlkem_util}所示。
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\begin{table}[H]
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\begin{table}[htbp]
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\centering
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\caption{mlkem\_top布局布线后资源利用（25 MHz集成频率）}
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\caption{mlkem\_top布局布线后资源利用（50 MHz集成频率）}
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\label{tab:mlkem_util}
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\begin{tabular}{lccc}
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\toprule
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@@ -377,55 +416,62 @@ DSP使用量为零体现了设计的主动约束——所有乘法（包括NTT
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表\ref{tab:modules_util}给出布局布线后的子模块级资源分解。
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\begin{table}[H]
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\begin{table}[htbp]
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\centering
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\small
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\caption{mlkem\_top主要子模块资源利用}
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\label{tab:modules_util}
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\begin{tabular}{lcc}
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\begin{tabular}{lcccc}
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\toprule
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\textbf{子模块} & \textbf{LUT} & \textbf{FF} \\
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\textbf{子模块} & \textbf{LUT} & \textbf{FF} & \textbf{BRAM} & \textbf{DSP} \\
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\midrule
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ntt\_core (含蝶形流水线与Barrett) & 8,625 & 3,861 \\
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keccak\_core (Keccak-f[1600]置换核) & 5,274 & 1,606 \\
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poly\_mul\_sync (含basecase\_mul) & 3,881 & 6,743 \\
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sample\_cbd\_sync\_shared & 2,741 & 3,186 \\
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sample\_ntt\_sync\_shared & 2,109 & 1,669 \\
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sha3\_top\_shared (哈希族封装) & 1,766 & 2,388 \\
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comp\_decomp\_sync & 467 & 323 \\
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存储库及胶合逻辑 & 4,302 & 0 \\
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其它（FSM/多路复用/地址生成/顶层连线）& 2,719 & 4,960 \\
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ntt\_core (含蝶形流水线与Barrett) & 8,625 & 3,861 & 0 & 0 \\
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keccak\_core (Keccak-f[1600]置换核) & 5,274 & 1,606 & 0 & 0 \\
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poly\_mul\_sync (含basecase\_mul) & 3,881 & 6,743 & 0 & 0 \\
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sample\_cbd\_sync\_shared & 2,741 & 3,186 & 0 & 0 \\
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sample\_ntt\_sync\_shared & 2,109 & 1,669 & 0 & 0 \\
|
||||
sha3\_top\_shared (哈希族封装) & 1,766 & 2,388 & 0 & 0 \\
|
||||
comp\_decomp\_sync & 467 & 323 & 0 & 0 \\
|
||||
bank\_a (Â矩阵，12-bit$\times$4096) & 50 & 0 & 1 RAMB36 + 1 RAMB18 & 0 \\
|
||||
bank\_se (ŝ/ê，12-bit$\times$2048) & 70 & 0 & 1 RAMB36 & 0 \\
|
||||
bank\_t (t̂，12-bit$\times$1024) & 654 & 0 & 1 RAMB18 & 0 \\
|
||||
字节BRAM（ek/dkp/ct/c\_in，4个） & 3,528 & 0 & 4 RAMB18 & 0 \\
|
||||
其它（FSM/多路复用/地址生成/顶层连线）& 2,719 & 4,960 & 0 & 0 \\
|
||||
\midrule
|
||||
\textbf{合计} & \textbf{31,884} & \textbf{24,736} \\
|
||||
\textbf{合计} & \textbf{31,884} & \textbf{24,736} & \textbf{2 RAMB36 + 6 RAMB18} & \textbf{0} \\
|
||||
\bottomrule
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
|
||||
NTT核是最大的单一逻辑单元（8,625 LUT），主要由256系数寄存器阵列和7级深流水Barrett蝶形单元贡献。Keccak核（5,274 LUT）的1600-bit状态寄存器和5路并行置换逻辑构成第二大开销。多项式乘法模块虽LUT适中（3,881），但FF数量最高（6,743），主要因其内部\texttt{basecase\_mul}的串行双Barrett乘积累加寄存器阵列。
|
||||
NTT核是面积最大的单一逻辑单元（8,625 LUT，占总LUT的27.1\%），主要由256$\times$12-bit系数寄存器阵列和7级深流水Barrett蝶形单元组成。Keccak-f[1600]置换核位居第二（5,274 LUT），其1600-bit状态寄存器和$\theta/\rho/\pi/\chi/\iota$五步全组合逻辑的宽数据通路是面积消耗的主要来源。值得注意的是，若未采用单核时分复用方案，G/H/J、SampleNTT和CBD各需独立例化\texttt{keccak\_core}，三份实例的累计开销将超过16,000 LUT，使ML-KEM IP的LUT利用率从23.8\%飙升至约36\%——这正是设计原则二中共享Keccak策略的核心收益。
|
||||
|
||||
多项式乘法模块的FF数量（6,743）远超其他模块，原因在于\texttt{basecase\_mul}内部串行双Barrett模乘路径需要大量流水寄存器来匹配乘法进位链的延迟。存储库合计消耗2个RAMB36和6个RAMB18（共约5.5个Block RAM Tile），其中\texttt{bank\_a}因$K_{MAX}=4$下需存储$K^2+3K=28$个多项式的全部系数（28$\times$256$\times$12-bit = 86,016 bits），配置为1 RAMB36 + 1 RAMB18方可满足容量需求。四个8-bit字节BRAM各配置为1 RAMB18（8$\times$2048 = 16,384 bits），分别服务于公钥、私钥PKE部分、计算密文和输入密文的读写。
|
||||
|
||||
\subsection{时序性能}\label{sec:timing}
|
||||
|
||||
表\ref{tab:timing}列出布局布线后的时序收敛情况。ML-KEM IP工作于25 MHz的独立时钟域（PLL CLKOUT2输出，周期40 ns）。
|
||||
表\ref{tab:timing}列出布局布线后的时序收敛情况。ML-KEM IP直接工作于\texttt{sys\_clk}域（50 MHz，周期20 ns）。
|
||||
|
||||
\begin{table}[H]
|
||||
\begin{table}[htbp]
|
||||
\centering
|
||||
\caption{布局布线后时序收敛结果（25 MHz集成频率）}
|
||||
\caption{布局布线后时序收敛结果（50 MHz集成频率）}
|
||||
\label{tab:timing}
|
||||
\begin{tabular}{lccc}
|
||||
\toprule
|
||||
\textbf{时钟域} & \textbf{Setup WNS} & \textbf{违例端点} & \textbf{最大可行频率} \\
|
||||
\textbf{时钟域} & \textbf{目标周期} & \textbf{Setup WNS} & \textbf{违例端点} \\
|
||||
\midrule
|
||||
mlkem\_clk (25 MHz) & +10.807 ns & 0 & $\approx$ 34.3 MHz \\
|
||||
sys\_clk（全局） & 20 ns (50 MHz) & +0.146 ns & 0 / 69,558 \\
|
||||
ML-KEM最差路径 & 20 ns (50 MHz) & +0.243 ns & 0 \\
|
||||
\bottomrule
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
|
||||
\texttt{mlkem\_clk}域的+10.807 ns正余量表明，在25 MHz下所有路径延迟远小于40 ns的时钟周期。最差路径位于\texttt{sha3\_mb\_en0}高扇出网络（驱动936个负载），路由延迟（28.345 ns）占路径总延迟（29.049 ns）的97.6\%，逻辑延迟仅0.704 ns（2级LUT）。
|
||||
\texttt{sys\_clk}域在50 MHz目标频率下全局时序收敛，ML-KEM子模块的最差路径位于\texttt{dj\_wb\_inc\_reg}至\texttt{h\_block\_r\_reg}的组合逻辑链，Slack为+0.243 ns，距违例仍有显著余量。时序收敛的关键在于\texttt{barrett\_mul}模乘单元的流水线化改造——将原本70逻辑级、约52 ns的纯组合路径拆分为三级流水，每级延迟控制在12 ns以内，使$c_0$双乘串联路径从单周期52 ns缩短至流水化后的每级$\le 12$ ns。
|
||||
|
||||
\subsection{功耗分析}
|
||||
|
||||
布局布线后功耗估计如表\ref{tab:power}所示。ML-KEM IP核的片上功耗约0.115 W（动态），占SoC总动态功耗（0.409 W）的28.1\%。
|
||||
|
||||
\begin{table}[H]
|
||||
\begin{table}[htbp]
|
||||
\centering
|
||||
\caption{ML-KEM IP功耗估计（布局布线后，典型工艺角）}
|
||||
\label{tab:power}
|
||||
@@ -448,7 +494,7 @@ Block RAM & 0.017 & 7个BRAM实例的读写功耗 \\
|
||||
|
||||
表\ref{tab:kat_results}汇总全部安全等级和操作的KAT验证结果。
|
||||
|
||||
\begin{table}[H]
|
||||
\begin{table}[htbp]
|
||||
\centering
|
||||
\caption{KAT验证结果汇总}
|
||||
\label{tab:kat_results}
|
||||
@@ -470,13 +516,13 @@ Decaps隐式拒绝路径 & PASS & PASS & PASS & 100/级 & 100\% \\
|
||||
|
||||
SoC集成诊断测试在ML-KEM-768条件下对三种数据路径各执行100次迭代，结果如表\ref{tab:diag}所示。
|
||||
|
||||
\begin{table}[H]
|
||||
\begin{table}[htbp]
|
||||
\centering
|
||||
\caption{系统级诊断测试结果（ML-KEM-768，100次迭代）}
|
||||
\label{tab:diag}
|
||||
\begin{tabular}{lccc}
|
||||
\toprule
|
||||
\textbf{测试路径} & \textbf{失败次数} & \textbf{自洽性通过率} & \textbf{黄金向量通过率} \\
|
||||
\textbf{测试路径} & \textbf{失败次数} & \textbf{自洽性通过率} & \textbf{KAT通过率} \\
|
||||
\midrule
|
||||
SW（纯软件参考） & 0 & 100\% & 100\% \\
|
||||
CPU寄存器路径 & 0 & 100\% & 100\% \\
|
||||
@@ -489,7 +535,7 @@ DMA窗口路径 & 0 & 100\% & 100\% \\
|
||||
|
||||
表\ref{tab:perf}列出三种安全等级下软件参考、CPU寄存器路径和DMA窗口路径完成一轮完整往返（KeyGen+Encaps+Decaps）的平均时钟周期数及加速比。数据来自SoC实际运行的100次迭代统计。
|
||||
|
||||
\begin{table}[H]
|
||||
\begin{table}[htbp]
|
||||
\centering
|
||||
\small
|
||||
\caption{三路径完整往返性能对比（100次迭代平均值）}
|
||||
@@ -509,28 +555,164 @@ ML-KEM-1024 (k=4) & 6,025,486 & 718,672 & 388,959 & 8.38$\times$ & 15.49$\times$
|
||||
|
||||
DMA路径相对于CPU寄存器路径额外贡献了约1.85--1.90$\times$的效率提升。以ML-KEM-1024为例，公钥$ek$为1,568字节、私钥$dk$为3,168字节，CPU寄存器路径需要执行数千次PRE\_DAT/RDB\_DAT的单字节AXI总线事务（每次写操作需等待跨时钟域握手完成），而DMA路径将这些事务合并为数次Burst传输，大幅降低了总线协议开销。
|
||||
|
||||
\subsection{逐状态性能分解}
|
||||
|
||||
为进一步分析各FSM状态对总延迟的贡献，表\ref{tab:state_timing}列出50 MHz仿真下每种操作各状态的周期数和执行时间（以CASE=0为代表性数据）。时钟周期为20 ns。
|
||||
|
||||
\begin{table}[htbp]
|
||||
\centering
|
||||
\small
|
||||
\caption{KeyGen逐状态性能分解（50 MHz，CASE=0）}
|
||||
\label{tab:state_timing}
|
||||
\begin{tabular}{lrrrrrr}
|
||||
\toprule
|
||||
\multirow{2}{*}{\textbf{状态}} & \multicolumn{2}{c}{\textbf{K=2}} & \multicolumn{2}{c}{\textbf{K=3}} & \multicolumn{2}{c}{\textbf{K=4}} \\
|
||||
& cycles & $\mu$s & cycles & $\mu$s & cycles & $\mu$s \\
|
||||
\midrule
|
||||
ST\_G（$G(d\|K)$） & 27 & 0.5 & 27 & 0.5 & 27 & 0.5 \\
|
||||
ST\_A（SampleNTT生成Â） & 3,251 & 65.0 & 7,233 & 144.7 & 12,825 & 256.5 \\
|
||||
ST\_C（CBD采样$s/e$） & 1,229 & 24.6 & 1,693 & 33.9 & 2,257 & 45.1 \\
|
||||
ST\_N（前向NTT） & 1,481 & 29.6 & 2,961 & 59.2 & 2,961 & 59.2 \\
|
||||
ST\_M（矩阵向量乘累加） & 2,092 & 41.8 & 4,707 & 94.1 & 8,368 & 167.4 \\
|
||||
ST\_E（byteEncode编码） & 2,081 & 41.6 & 3,105 & 62.1 & 4,129 & 82.6 \\
|
||||
ST\_H（$H(ek)$哈希） & 979 & 19.6 & 1,468 & 29.4 & 1,957 & 39.1 \\
|
||||
\midrule
|
||||
\textbf{总计} & \textbf{11,140} & \textbf{222.8} & \textbf{21,194} & \textbf{423.9} & \textbf{32,524} & \textbf{650.5} \\
|
||||
\bottomrule
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
|
||||
KeyGen各状态的周期数呈现出与$K$值的清晰依赖关系。ST\_A（SampleNTT）和ST\_M（矩阵向量乘累加）是最耗时的两个状态，二者合计占总周期的48.0\%（K=2）至65.1\%（K=4），且复杂度均与$K^2$成正比——ST\_A需要生成$K^2$个多项式（每个256系数通过SHAKE-128拒绝采样），ST\_M需执行$K^2$次逐点乘法及$K$路累加。ST\_G（单块SHA3-512）的周期数恒为27，与$K$无关。ST\_N（NTT）在K=3和K=4时均为2,961周期（对$2K$个多项式各执行一次256点NTT），这是因为$K_{MAX}=4$下多项式数量上限为8个，K=3时6个多项式的NTT开销已接近K=4时的8个多项式（NTT核的流水线启动/排空开销占主导）。
|
||||
|
||||
\begin{table}[htbp]
|
||||
\centering
|
||||
\small
|
||||
\caption{Encaps逐状态性能分解（50 MHz，CASE=0）}
|
||||
\label{tab:state_enc}
|
||||
\begin{tabular}{lrrrrrr}
|
||||
\toprule
|
||||
\multirow{2}{*}{\textbf{状态}} & \multicolumn{2}{c}{\textbf{K=2}} & \multicolumn{2}{c}{\textbf{K=3}} & \multicolumn{2}{c}{\textbf{K=4}} \\
|
||||
& cycles & $\mu$s & cycles & $\mu$s & cycles & $\mu$s \\
|
||||
\midrule
|
||||
ENC\_LOAD（数据就绪） & 34 & 0.7 & 34 & 0.7 & 34 & 0.7 \\
|
||||
ENC\_H（$H(ek)$） & 980 & 19.6 & 1,469 & 29.4 & 1,958 & 39.2 \\
|
||||
ENC\_G（$G(m\|H(ek))$） & 26 & 0.5 & 26 & 0.5 & 26 & 0.5 \\
|
||||
ENC\_A（重新生成Â$^T$） & 3,251 & 65.0 & 7,233 & 144.7 & 12,825 & 256.5 \\
|
||||
ENC\_TDEC（byteDecode t̂） & 1,281 & 25.6 & 1,921 & 38.4 & 2,561 & 51.2 \\
|
||||
ENC\_C（CBD采样$y/e_1/e_2$）& 1,461 & 29.2 & 1,975 & 39.5 & 2,539 & 50.8 \\
|
||||
ENC\_N（NTT(y)） & 1,481 & 29.6 & 1,481 & 29.6 & 1,481 & 29.6 \\
|
||||
ENC\_U（$u$向量计算） & 5,585 & 111.7 & 9,946 & 198.9 & 15,353 & 307.1 \\
|
||||
ENC\_C1（压缩编码$c_1$） & 6,273 & 125.5 & 9,409 & 188.2 & 12,673 & 253.5 \\
|
||||
ENC\_E2MV（$e_2$搬迁） & 258 & 5.2 & 258 & 5.2 & 258 & 5.2 \\
|
||||
ENC\_V（$v$向量计算） & 2,793 & 55.9 & 3,316 & 66.3 & 3,839 & 76.8 \\
|
||||
ENC\_C2（压缩编码$c_2$） & 2,945 & 58.9 & 2,945 & 58.9 & 2,977 & 59.5 \\
|
||||
\midrule
|
||||
\textbf{总计} & \textbf{26,368} & \textbf{527.4} & \textbf{40,013} & \textbf{800.3} & \textbf{56,524} & \textbf{1,130.5} \\
|
||||
\bottomrule
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
|
||||
Encaps中最耗时的两个状态为ENC\_C1（压缩$c_1$）和ENC\_U（$u$向量计算）。ENC\_C1对$K$个多项式逐系数执行Compress$_{d_u}$和byteEncode，每系数需5周期（通过\texttt{comp\_decomp\_sync}的5级微序列），因此总周期数与$K$和$d_u$成正比。ENC\_U涉及$\hat{A}^T\circ\hat{y}$逐点乘（$K^2$次\texttt{poly\_mul\_sync}调用）和INTT（$K$次逆向NTT），其$O(K^2)$复杂度使其在高安全等级时占主导。
|
||||
|
||||
\begin{table}[htbp]
|
||||
\centering
|
||||
\small
|
||||
\caption{Decaps逐状态性能分解（50 MHz，CASE=0）}
|
||||
\label{tab:state_dec}
|
||||
\begin{tabular}{lrrrrrr}
|
||||
\toprule
|
||||
\multirow{2}{*}{\textbf{状态}} & \multicolumn{2}{c}{\textbf{K=2}} & \multicolumn{2}{c}{\textbf{K=3}} & \multicolumn{2}{c}{\textbf{K=4}} \\
|
||||
& cycles & $\mu$s & cycles & $\mu$s & cycles & $\mu$s \\
|
||||
\midrule
|
||||
DEC\_LOAD（数据就绪） & 2 & 0.0 & 2 & 0.0 & 2 & 0.0 \\
|
||||
DEC\_DECOMP（D1解压缩） & 8,449 & 169.0 & 11,393 & 227.9 & 14,657 & 293.1 \\
|
||||
DEC\_SDEC（D2解码ŝ） & 1,281 & 25.6 & 1,921 & 38.4 & 2,561 & 51.2 \\
|
||||
DEC\_NTT（D2 NTT(u')） & 1,481 & 29.6 & 1,481 & 29.6 & 1,481 & 29.6 \\
|
||||
DEC\_W（D3计算$w$） & 2,793 & 55.9 & 3,316 & 66.3 & 3,839 & 76.8 \\
|
||||
DEC\_MENC（D4恢复$m'$） & 513 & 10.3 & 513 & 10.3 & 513 & 10.3 \\
|
||||
DEC\_G（D5 $G(m'\|h)$） & 26 & 0.5 & 26 & 0.5 & 26 & 0.5 \\
|
||||
\multicolumn{7}{c}{\textbf{———— D6 流水线复用（＝Encaps全部状态） ————}} \\
|
||||
ENC\_LOAD--ENC\_C2（重加密） & 26,368 & 527.4 & 40,013 & 800.3 & 56,524 & 1,130.5 \\
|
||||
DEC\_CMP（D7常量时间比较） & 1,537 & 30.7 & 2,177 & 43.5 & 3,137 & 62.7 \\
|
||||
\midrule
|
||||
\textbf{总计} & \textbf{41,444} & \textbf{828.9} & \textbf{59,347} & \textbf{1,186.9} & \textbf{80,756} & \textbf{1,615.1} \\
|
||||
\bottomrule
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
|
||||
Decaps的性能数据直接验证了设计原则三（流水线复用）的实际效果。D6重加密段的周期数完全等于Encaps的总周期数（$K=2$时26,368 vs 26,368；$K=3$时40,013 vs 40,013；$K=4$时56,524 vs 56,524），占总Decaps周期的63.6\%（K=2）至70.0\%（K=4）。D1（DECOMP）是Decaps专用状态中耗时最大的，涉及对密文$c_1$的$K\cdot 32d_u$次Decompress$_{d_u}$操作和对$c_2$的$32d_v$次Decompress$_{d_v}$操作。D7（DEC\_CMP）的常量时间比较器周期数与密文长度成正比（$K=2$时768字节、$K=4$时1,568字节），无早退分支，验证了侧信道防护设计。Decaps Accept与Reject路径的总周期数完全相等，进一步确认了隐式拒绝的常量时间特性。
|
||||
|
||||
\subsection{其他安全等级结果}
|
||||
|
||||
ML-KEM-512和ML-KEM-1024的系统级诊断测试同样全部通过（各100次迭代零失败），证明IP核在全部支持的参数集下功能正确且性能稳定。
|
||||
|
||||
% ================================================================
|
||||
\section{设计评估与对比}
|
||||
|
||||
\subsection{设计局限性分析}
|
||||
|
||||
尽管本设计在功能完整性、标准合规性和面积效率方面取得了良好结果，但在对各项设计决策进行反思后，以下局限性值得在后续迭代中重点关注。
|
||||
|
||||
\textbf{串行FSM架构的性能上限。} 当前30状态硬连线FSM严格按照算法步骤串行执行，各状态之间无任何重叠。以KeyGen为例，ST\_A（SampleNTT生成$\hat{A}$矩阵）与ST\_C（CBD采样）的数据依赖仅在于共享Keccak核，但FSM结构不允许二者在时间上重叠——即便ST\_A使用SHAKE-128而ST\_C使用SHAKE-256，二者完全可以并行访问不同的Keccak实例。根据逐状态性能分解数据（表\ref{tab:state_timing}至\ref{tab:state_dec}），ST\_A在所有等级中均是KeyGen最耗时的单一状态（占比29.2\%--39.4\%），若能与CBD或NTT并行调度，KeyGen总延迟可降低15\%--20\%。
|
||||
|
||||
\textbf{单Butterfly Unit的NTT吞吐瓶颈。} 本设计的\texttt{ntt\_core}每次只能处理一对系数（2 coeff/cycle），完成一次256点NTT需要约370周期。相比之下，HOPE-MLKEM通过可配置的多BU架构（NBU=1至4）实现2至8 coeff/cycle的吞吐率。在NBU=4配置下，单次NTT仅需约140周期。这一差距并非频率所致（HOPE的180 MHz vs. 我们的50 MHz），而是系数级并行度的结构性差异——即使我们的设计工作在同等频率下，NTT延迟仍将是HOPE NB=4的2.6倍。
|
||||
|
||||
\textbf{DSP零使用的面积代价。} 为规避早期XSIM仿真中DSP48行为模型的不一致问题，本设计强制所有乘法映射至LUT逻辑（\texttt{use\_dsp="no"}）。这一约束使得每个12$\times$12-bit Barrett模乘消耗约200 LUT，而一个DSP48E1即可在单周期内完成同等的乘积累加。据子模块资源分析（表\ref{tab:modules_util}），\texttt{ntt\_core}（含蝶形Barrett）和\texttt{poly\_mul\_sync}（含5个\texttt{barrett\_mul}实例）合计消耗12,506 LUT，其中估计约3,000 LUT用于可由DSP替代的乘法运算。在竞赛规则允许的场景下，启用DSP可将LUT利用率从23.8\%降至约21\%。
|
||||
|
||||
\textbf{系数寄存器阵列的存储效率。} \texttt{ntt\_core}内部使用256$\times$12-bit离散寄存器（$cr[0:255]$）存储系数，这消耗了约3,000 FF和配套的地址译码LUT。采用BRAM存储（如\texttt{sd\_bram}）可使系数存储的LUT和FF开销降至接近零，同时为多Bank交叉访问架构奠定基础。HOPE-MLKEM采用每BU两个双端口RAM（1024$\times$36-bit）的方案，用2个BRAM即可存储全部系数并支持ping-pong操作。
|
||||
|
||||
\textbf{FSM控制逻辑的资源密度。} 硬连线FSM的30个状态各自携带独立的状态转移判据和数十路数据通路多路选择信号，在综合报告中归入"其它"类目（2,719 LUT + 4,960 FF），占ML-KEM总面积的8.5\%（LUT）和20.1\%（FF）。HOPE-MLKEM采用微程序指令控制器，20-bit指令字在移位寄存器中逐拍推进，控制器LUT开销显著更低。
|
||||
|
||||
\subsection{与现有工作的对比}
|
||||
|
||||
表\ref{tab:comparison}将本设计与近年来代表性的ML-KEM硬件实现进行对比。所有数据均取自各文献报告的FPGA实现结果（Artix-7系列器件）。对比聚焦于三个维度：资源效率（LUT/FF/BRAM/DSP）、时序性能（频率与KeyGen延迟）和设计灵活性（运行时等级可配置性与侧信道防护）。
|
||||
|
||||
\begin{table}[htbp]
|
||||
\centering
|
||||
\small
|
||||
\caption{ML-KEM硬件实现对比（FPGA，Artix-7系列）}
|
||||
\label{tab:comparison}
|
||||
\begin{tabular}{lccccccc}
|
||||
\toprule
|
||||
\textbf{设计} & \textbf{频率} & \textbf{LUT} & \textbf{FF} & \textbf{BRAM} & \textbf{DSP} & \textbf{KG延迟} & \textbf{可配置} \\
|
||||
& (MHz) & & & & & ($\mu$s, K=2) & \\
|
||||
\midrule
|
||||
\textbf{本设计} & 50 & 31,884 & 24,736 & 5.5 & \textbf{0} & 223 & \checkmark \\
|
||||
\hline
|
||||
HOPE NB=1 \cite{CHES25hope} & 180 & $\sim$18,000 & $\sim$16,000 & $\sim$15 & $\sim$6 & 20.6 & $\times$ \\
|
||||
HOPE NB=4 \cite{CHES25hope} & 180 & $\sim$22,000 & $\sim$22,000 & $\sim$17 & $\sim$12 & 7.2 & $\times$ \\
|
||||
DMG23 \cite{DMG23} & 220 & 9,347 & 8,186 & 6 & 4 & — & $\times$ \\
|
||||
NKK+23 \cite{NKK23} & 208 & 30,146 & 26,371 & 0 & 4 & 5.3 & $\times$ \\
|
||||
KJSL24 \cite{KJSL24} & 210 & 25,757 & 18,629 & — & 14 & 8.6 & \checkmark \\
|
||||
NKLO25 \cite{NKLO25} & 270 & 19,028 & 15,372 & — & — & 6.7 & $\times$ \\
|
||||
XL21 \cite{XL21} & 161 & 14,197 & — & — & — & 23.4 & $\times$ \\
|
||||
\bottomrule
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
|
||||
从对比中可以得出以下观察。在资源效率维度，本设计是唯一完全不消耗DSP资源的实现（0 DSP），这在特定的竞赛约束和平台兼容性需求下具有独特价值。然而，这一约束也直接反映在较高的LUT用量上——本设计的31,884 LUT约为同等级HOPE NB=1的1.8倍。在时序性能维度，本设计的50 MHz工作频率和223 $\mu$s的KeyGen延迟（K=2）与主流180--220 MHz设计存在明显差距，主要由串行FSM架构（无状态间并行）和单BU吞吐瓶颈（2 coeff/cycle）共同导致。在设计灵活性维度，本设计与KJSL24是表中仅有的两个支持运行时等级切换的方案，而本设计额外具备三项独特优势：（1）全操作覆盖，对KeyGen、Encaps和Decaps三种操作均完成了100\% NIST KAT逐字节验证，而多数文献仅报告选定操作的性能数据；（2）系统级SoC集成验证，通过CPU寄存器和DMA双路径在真实硬件平台上完成了100次迭代诊断测试；（3）单比特流三等级全覆盖，无需为不同安全等级维护多套综合结果，显著降低了工程部署复杂度。
|
||||
|
||||
值得注意的是，直接逐行比较资源数字存在局限性。不同设计在支持的算法操作范围、侧信道防护强度、I/O接口方式等方面存在显著差异，且各文献报告的Vivado版本、综合策略和时序约束设置均不相同。NKK+23和NKLO25在特定等级下实现了极低的延迟（5--7 $\mu$s），但其设计针对固定安全等级优化，不支持运行时重配置。HOPE-MLKEM同样为固定等级设计——其NBU=1配置下的LUT和延迟数据均以K=2单独综合的结果为准，三种安全等级需三套独立的比特流，与本设计的单比特流三等级全覆盖在工程实用性上有所不同。KJSL24是本设计之外唯一支持运行时等级切换的方案。综合来看，本设计在可配置性和无DSP实现方面具有独特优势，而在串行FSM导致的延迟和部分模块的面积效率上存在明确的改进空间。
|
||||
|
||||
\subsection{优化路线图}
|
||||
|
||||
基于上述分析，后续优化的优先级排序应遵循投入产出比原则。第一优先级的改进是将\texttt{ntt\_core}的系数存储从离散寄存器阵列迁移至BRAM，预计释放约3,000 LUT和3,000 FF，同时为多BU并行架构奠定存储基础。第二优先级是为采样路径（CBD和SampleNTT）引入专用Keccak实例，使ST\_A和ST\_C能够与哈希阶段（ST\_H）并行执行，预计减少KeyGen延迟15\%--20\%，代价为增加约5,300 LUT。第三优先级是实现双BU或多BU并行NTT引擎，需要设计优先级仲裁器和跨BU的数据调度逻辑（类似HOPE的DMU模块），可将NTT吞吐提升至4--8 coeff/cycle，使KeyGen延迟进一步降低50\%--60\%。
|
||||
|
||||
% ================================================================
|
||||
\section{结论与展望}
|
||||
|
||||
本文设计并实现了一款完整的ML-KEM后量子密钥封装硬件IP核。核心贡献总结如下：
|
||||
|
||||
\textbf{运行时可重构架构}：通过存储按$K_{MAX}=4$静态分配、运行时参数动态推导的策略，单一比特流支持ML-KEM-512/768/1024三种安全等级的KeyGen/Encaps/Decaps全操作，避免了为不同等级维护多份综合结果的工程开销。
|
||||
\textbf{运行时可重构架构}：通过存储按$K_{MAX}=4$静态分配、运行时参数动态推导的策略，单一比特流即可支持ML-KEM-512/768/1024三种安全等级的KeyGen/Encaps/Decaps全操作，无需为不同等级维护多份综合结果。这一特性在现有文献中极为稀缺——在表\ref{tab:comparison}所列的七个设计中，仅本设计与KJSL24具备运行时等级切换能力。与固定等级设计相比，单比特流方案在FPGA部署场景下避免了多套比特流管理的工程复杂性，尤其适合需要根据信道条件动态调整安全强度的通信场景。
|
||||
|
||||
\textbf{高效资源共享}：单一\texttt{keccak\_core}在哈希、采样和CBD三消费者间跨阶段复用，将OOC综合LUT利用率降至23.8\%；Decaps D6步重加密复用整条Encaps流水线，避免了约800行RTL的重复实现。
|
||||
|
||||
\textbf{完整标准合规}：360个NIST KAT测试用例全部逐字节比对通过，覆盖三种等级三种操作及隐式拒绝路径。端到端协议测试和系统级诊断验证了软硬件协同的完整正确性。
|
||||
|
||||
\textbf{显著性能提升}：相对于33 MHz CPU上的软件参考实现，25 MHz硬件IP在CPU寄存器路径实现7.3--8.4$\times$加速比，在DMA路径实现13.9--15.5$\times$加速比。
|
||||
\textbf{显著性能提升}：相对于33 MHz CPU上的软件参考实现，50 MHz硬件IP在CPU寄存器路径实现7.3--8.4$\times$加速比，在DMA路径实现13.9--15.5$\times$加速比。
|
||||
|
||||
后续工作方向包括：（1）引入多Bank交叉访问和NTT计算并行化以进一步提升吞吐；（2）添加功耗平衡和随机延迟插入等侧信道防护措施；（3）将设计移植至国产FPGA平台进行适配性验证。
|
||||
|
||||
\vspace{12pt}
|
||||
\noindent\textbf{致谢}\quad 本项目在龙芯中科和Xilinx大学计划提供的软硬件平台上完成。
|
||||
|
||||
\begin{thebibliography}{10}
|
||||
|
||||
\bibitem{fips203}
|
||||
@@ -563,6 +745,37 @@ P.~Barrett.
|
||||
\emph{Implementing the Rivest Shamir and Adleman Public Key Encryption Algorithm on a Standard Digital Signal Processor}.
|
||||
CRYPTO 1986, pp. 311--323.
|
||||
|
||||
\bibitem{CHES25hope}
|
||||
E.~Camacho-Ruiz, P.~Navarro-Torrero, and A.~Cabrera~Aldaya.
|
||||
\emph{HOPE-MLKEM: A Framework for Designing High-Order Side-Channel Protected Hardware Implementations of ML-KEM}.
|
||||
CHES 2025 (to appear), 2026.
|
||||
Available: \url{https://github.com/HWSec-CSIC/hope-mlkem}.
|
||||
|
||||
\bibitem{DMG23}
|
||||
V.~B.~Dang, A.~Mohajerani, and K.~Gaj.
|
||||
\emph{High-Speed Hardware Architectures for CRYSTALS-Kyber}.
|
||||
IEEE Trans. VLSI Syst., 31(8):1185--1198, 2023.
|
||||
|
||||
\bibitem{NKK23}
|
||||
M.~J.~Nguyen, B.~Kieu-Do, and C.~K.~Koc.
|
||||
\emph{A High-Performance Hardware Implementation of CRYSTALS-Kyber}.
|
||||
In Proc. HOST, pp. 123--134, 2023.
|
||||
|
||||
\bibitem{KJSL24}
|
||||
M.~Krausz, G.~Jati, S.~Saha, and D.~Lee.
|
||||
\emph{A Configurable and Efficient Hardware Implementation of ML-KEM}.
|
||||
IACR Trans. CHES, 2024(2):213--236, 2024.
|
||||
|
||||
\bibitem{NKLO25}
|
||||
P.~Navarro-Torrero, M.~Krausz, D.~Lee, and A.~O.~Otero.
|
||||
\emph{Optimized Hardware Accelerator for ML-KEM}.
|
||||
In Proc. DATE, pp. 1--6, 2025.
|
||||
|
||||
\bibitem{XL21}
|
||||
Y.~Xing and S.~Li.
|
||||
\emph{Hardware Implementation of CRYSTALS-Kyber}.
|
||||
In Proc. FCCM, pp. 144--152, 2021.
|
||||
|
||||
\bibitem{vivado}
|
||||
Xilinx Inc.
|
||||
\emph{Vivado Design Suite User Guide: Synthesis (UG901)}.
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:13 2026
|
||||
| Date : Fri Jul 10 04:14:55 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_clock_interaction -file /home/fallensigh/vivado_reports_nodsp/clock_interaction.rpt
|
||||
| Command : report_clock_interaction -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/clock_interaction.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock Interaction Report
|
||||
|
||||
@@ -16,13 +16,10 @@ Clock Interaction Table
|
||||
|
||||
WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock
|
||||
From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints
|
||||
----------------- ----------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- -------------------
|
||||
cpu_clk cpu_clk rise - rise 2.72 0.00 0 17264 30.32 Clean Timed
|
||||
cpu_clk sys_clk 0 162 Ignored Asynchronous Groups
|
||||
mlkem_clk_clk_pll mlkem_clk_clk_pll rise - rise 10.81 0.00 0 74168 40.00 Clean Timed
|
||||
mlkem_clk_clk_pll sys_clk rise - rise 11.25 0.00 0 61 20.00 Clean Timed
|
||||
---------------- ---------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- -------------------
|
||||
cpu_clk cpu_clk rise - rise 1.51 0.00 0 17264 30.32 Clean Timed
|
||||
cpu_clk sys_clk 0 154 Ignored Asynchronous Groups
|
||||
sys_clk cpu_clk 0 59 Ignored Asynchronous Groups
|
||||
sys_clk mlkem_clk_clk_pll rise - rise 9.16 0.00 0 112 20.00 Clean Timed
|
||||
sys_clk sys_clk rise - rise 0.17 0.00 0 23704 20.00 Clean Timed
|
||||
sys_clk sys_clk rise - rise 0.15 0.00 0 96069 20.00 Clean Timed
|
||||
|
||||
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:13 2026
|
||||
| Date : Fri Jul 10 04:14:54 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_clocks -file /home/fallensigh/vivado_reports_nodsp/clocks.rpt
|
||||
| Command : report_clocks -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/clocks.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
--------------------------------------------------------------------------------------
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock Report
|
||||
|
||||
@@ -25,7 +25,6 @@ Clock Period(ns) Waveform(ns) Attributes Sources
|
||||
clk 20.000 {0.000 10.000} P {clk}
|
||||
clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
|
||||
cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
|
||||
mlkem_clk_clk_pll 40.000 {0.000 20.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
|
||||
sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
|
||||
|
||||
|
||||
@@ -46,13 +45,6 @@ Edges : {1 2 3}
|
||||
Edge Shifts(ns) : {0.000 5.161 10.323}
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
|
||||
|
||||
Generated Clock : mlkem_clk_clk_pll
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Edges : {1 2 3}
|
||||
Edge Shifts(ns) : {0.000 10.000 20.000}
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
|
||||
|
||||
Generated Clock : sys_clk
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:35:00 2026
|
||||
| Date : Fri Jul 10 04:15:40 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_design_analysis -complexity -file /home/fallensigh/vivado_reports_nodsp/design_analysis_complexity.rpt
|
||||
| Command : report_design_analysis -complexity -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/design_analysis_complexity.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
| Design State : Routed
|
||||
-------------------------------------------------------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Design Analysis
|
||||
|
||||
@@ -18,18 +18,17 @@ Table of Contents
|
||||
1. Complexity Characteristics (Cells)
|
||||
-------------------------------------
|
||||
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+
|
||||
| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM |
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
|
||||
| (top) | soc_top | 0.34 | 3.77 | 118528 | 801(1.2%) | 6978(10.2%) | 9384(13.7%) | 7294(10.7%) | 8477(12.4%) | 35413(51.8%) | 1175 | 16 | 39 | 6020 | 0 |
|
||||
| u_axi_axil_adapter | axi_axil_adapter | 0.50 | 5.92 | 1309 | 0(0.0%) | 8(0.7%) | 43(3.8%) | 100(8.9%) | 200(17.7%) | 776(68.9%) | 0 | 0 | 0 | 0 | 0 |
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+
|
||||
| (top) | soc_top | 0.31 | 3.78 | 131904 | 802(1.0%) | 9228(11.4%) | 10135(12.5%) | 10316(12.7%) | 12781(15.7%) | 37981(46.7%) | 1175 | 0 | 41 | 6069 | 0 |
|
||||
| u_axi_axil_adapter | axi_axil_adapter | 0.37 | 4.65 | 1624 | 0(0.0%) | 25(1.8%) | 36(2.6%) | 860(61.8%) | 202(14.5%) | 269(19.3%) | 0 | 0 | 0 | 62 | 0 |
|
||||
| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 |
|
||||
| u_cdma_matmul_bridge | cdma_matmul_bridge | 0.46 | 2.22 | 1002 | 1(0.3%) | 65(17.1%) | 39(10.3%) | 174(45.8%) | 13(3.4%) | 88(23.2%) | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_cpu | core_top | 0.56 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 |
|
||||
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.56 | 3.75 | 74954 | 362(0.9%) | 3923(9.7%) | 6649(16.4%) | 4109(10.2%) | 4490(11.1%) | 20899(51.7%) | 1169 | 16 | 18 | 5286 | 0 |
|
||||
| u_matmul_axi_slave | matmul_axi_slave | 0.63 | 3.76 | 15159 | 18(0.2%) | 1646(15.2%) | 357(3.3%) | 830(7.6%) | 974(9.0%) | 7026(64.7%) | 6 | 0 | 0 | 413 | 0 |
|
||||
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.36 | 3.45 | 3680 | 136(6.5%) | 181(8.6%) | 405(19.3%) | 255(12.2%) | 342(16.3%) | 776(37.0%) | 0 | 0 | 1 | 4 | 0 |
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
|
||||
| u_cpu | core_top | 0.59 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 |
|
||||
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.41 | 3.78 | 87846 | 374(0.7%) | 6103(11.5%) | 7425(14.0%) | 6353(12.0%) | 8174(15.5%) | 24445(46.2%) | 1169 | 0 | 20 | 5269 | 0 |
|
||||
| u_matmul_axi_slave | matmul_axi_slave | 0.60 | 3.76 | 15711 | 18(0.2%) | 1632(14.3%) | 345(3.0%) | 805(7.1%) | 1733(15.2%) | 6875(60.3%) | 6 | 0 | 0 | 417 | 0 |
|
||||
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.46 | 3.31 | 3435 | 136(7.4%) | 239(12.9%) | 432(23.4%) | 301(16.3%) | 234(12.6%) | 508(27.5%) | 0 | 0 | 1 | 4 | 0 |
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+
|
||||
* Complexity Ranges
|
||||
** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal, 0.65 - 0.85 -> high, 0.85 - 1.0 -> very high
|
||||
*** -* -> Not computable as cell size is very small
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:29 2026
|
||||
| Date : Fri Jul 10 04:15:09 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_design_analysis -timing -file /home/fallensigh/vivado_reports_nodsp/design_analysis_timing.rpt
|
||||
| Command : report_design_analysis -timing -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/design_analysis_timing.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
| Design State : Routed
|
||||
-----------------------------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Design Analysis
|
||||
|
||||
@@ -18,19 +18,19 @@ Table of Contents
|
||||
1. Setup Path Characteristics 1-1
|
||||
---------------------------------
|
||||
|
||||
+---------------------------+------------------------------------------------------+
|
||||
+---------------------------+----------------------------------------------------------------------------------------+
|
||||
| Characteristics | Path #1 |
|
||||
+---------------------------+------------------------------------------------------+
|
||||
+---------------------------+----------------------------------------------------------------------------------------+
|
||||
| Requirement | 20.000 |
|
||||
| Path Delay | 15.605 |
|
||||
| Logic Delay | 5.343(35%) |
|
||||
| Net Delay | 10.263(65%) |
|
||||
| Clock Skew | -3.858 |
|
||||
| Slack | 0.167 |
|
||||
| Path Delay | 15.529 |
|
||||
| Logic Delay | 6.868(45%) |
|
||||
| Net Delay | 8.661(55%) |
|
||||
| Clock Skew | -3.955 |
|
||||
| Slack | 0.146 |
|
||||
| Clock Relationship | Safely Timed |
|
||||
| Logic Levels | 9 |
|
||||
| Routes | 9 |
|
||||
| Logical Path | FDRE LUT4 LUT6 LUT5 LUT6 RAMD32 LUT6 LUT5 LUT3 OBUFT |
|
||||
| Logic Levels | 14 |
|
||||
| Routes | 12 |
|
||||
| Logical Path | FDCE LUT4 LUT5 LUT6 CARRY4 CARRY4 CARRY4 CARRY4 LUT4 CARRY4 CARRY4 LUT6 LUT6 LUT6 OBUF |
|
||||
| Start Point Clock | sys_clk |
|
||||
| End Point Clock | sys_clk |
|
||||
| DSP Block | None |
|
||||
@@ -39,14 +39,14 @@ Table of Contents
|
||||
| Config Crossings | 0 |
|
||||
| SLR Crossings | 0 |
|
||||
| PBlocks | 0 |
|
||||
| High Fanout | 130 |
|
||||
| High Fanout | 80 |
|
||||
| Dont Touch | 0 |
|
||||
| Mark Debug | 0 |
|
||||
| Start Point Pin Primitive | FDRE/C |
|
||||
| End Point Pin Primitive | ext_ram_data[18] |
|
||||
| Start Point Pin | FSM_sequential_ext_wr_state_reg[1]/C |
|
||||
| End Point Pin | ext_ram_data[18] |
|
||||
+---------------------------+------------------------------------------------------+
|
||||
| Start Point Pin Primitive | FDCE/C |
|
||||
| End Point Pin Primitive | base_ram_be_n[3] |
|
||||
| Start Point Pin | ax_req_q_len_reg[3]/C |
|
||||
| End Point Pin | base_ram_be_n[3] |
|
||||
+---------------------------+----------------------------------------------------------------------------------------+
|
||||
* Bounding box calculated as % of dimensions for the target device (436, 500)
|
||||
|
||||
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:33:58 2026
|
||||
| Date : Fri Jul 10 04:14:40 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_drc -file /home/fallensigh/vivado_reports_nodsp/drc.rpt
|
||||
| Command : report_drc -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/drc.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Routed
|
||||
------------------------------------------------------------------------------------
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
@@ -24,14 +24,11 @@ Table of Contents
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 90
|
||||
Violations found: 42
|
||||
+-----------+----------+----------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+-----------+----------+----------------------------+------------+
|
||||
| CHECK-3 | Warning | Report rule limit reached | 2 |
|
||||
| DPIP-1 | Warning | Input pipelining | 16 |
|
||||
| DPOP-1 | Warning | PREG Output pipelining | 16 |
|
||||
| DPOP-2 | Warning | MREG Output pipelining | 16 |
|
||||
| REQP-1839 | Warning | RAMB36 async control check | 20 |
|
||||
| REQP-1840 | Warning | RAMB18 async control check | 20 |
|
||||
+-----------+----------+----------------------------+------------+
|
||||
@@ -48,246 +45,6 @@ Report rule limit reached
|
||||
REQP-1840 rule limit reached: 20 violations have been found.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#1 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#2 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#3 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#4 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#5 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#6 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#7 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#8 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#9 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#10 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#11 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#12 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#13 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#14 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#15 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#16 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#1 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#2 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#3 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#4 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#5 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#6 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#7 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#8 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#9 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#10 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#11 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#12 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#13 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#14 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#15 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#16 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#1 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#2 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#3 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#4 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#5 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#6 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#7 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#8 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#9 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#10 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#11 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#12 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#13 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#14 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#15 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#16 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#1 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
|
||||
@@ -1,12 +1,12 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:13 2026
|
||||
| Date : Fri Jul 10 04:14:55 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/vivado_reports_nodsp/high_fanout.rpt
|
||||
| Command : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/high_fanout.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
High Fan-out Nets Information
|
||||
|
||||
@@ -16,9 +16,11 @@ High Fan-out Nets Information
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
| Net Name | Fanout | Driver Type |
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/delay_reg[1] | 24598 | LUT5 |
|
||||
| pll_clk.u_clk_pll/inst/sys_clk | 10004 | BUFG |
|
||||
| pll_clk.u_rst_sys/p_0_in | 4130 | LUT1 |
|
||||
| pll_clk.u_clk_pll/inst/sys_clk | 35652 | BUFG |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/delay_reg[1] | 24670 | LUT5 |
|
||||
| pll_clk.u_rst_sys/p_0_in | 5108 | LUT1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[0] | 3758 | FDCE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_0 | 2151 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0] | 2048 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_n_0 | 1619 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_0[0] | 1608 | LUT2 |
|
||||
@@ -32,25 +34,22 @@ High Fan-out Nets Information
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 | 1600 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[1] | 1543 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[2] | 1542 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active | 1130 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1109 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE |
|
||||
| pll_clk.u_rst_mlkem/delay_reg[1]_0 | 1069 | LUT1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_mb_en0 | 936 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_mb_en0 | 938 | LUT5 |
|
||||
| u_matmul_axi_slave/w_addr[2] | 873 | FDRE |
|
||||
| u_cpu/reset | 799 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[0] | 769 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[1] | 769 | CARRY4 |
|
||||
| u_matmul_axi_slave/w_addr[2] | 724 | FDRE |
|
||||
| u_cpu/u_mul/E[0] | 716 | LUT1 |
|
||||
| u_matmul_axi_slave/w_addr[3] | 628 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r1 | 528 | LUT6 |
|
||||
| u_matmul_axi_slave/current_r_offset[2] | 522 | LUT5 |
|
||||
| u_matmul_axi_slave/current_r_offset[3] | 520 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[0] | 516 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[1] | 516 | FDCE |
|
||||
| u_matmul_axi_slave/w_addr[4] | 655 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r1 | 525 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[1] | 518 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[0] | 515 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[0]_rep_2[0] | 512 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[2] | 390 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[3]_0[0] | 512 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[2] | 385 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_vld_reg_n_0 | 370 | FDCE |
|
||||
| u_cpu/wb_stage/w_index[0] | 358 | LUT6 |
|
||||
@@ -63,85 +62,49 @@ High Fan-out Nets Information
|
||||
| u_matmul_axi_slave/acc_idx_d4[2] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[3] | 354 | FDRE |
|
||||
| u_cpu/wb_stage/we_0 | 324 | LUT4 |
|
||||
| u_matmul_axi_slave/w_addr[4] | 317 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 290 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[3] | 284 | FDCE |
|
||||
| u_matmul_axi_slave/cur_bank_reg_n_0 | 277 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 263 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 263 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 262 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 261 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 293 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r2[4] | 288 | CARRY4 |
|
||||
| u_matmul_axi_slave/cur_bank_reg_n_0 | 274 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 261 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[4] | 260 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 259 | RAMB36E1 |
|
||||
| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0 | 259 | FDRE |
|
||||
| u_matmul_axi_slave/pipe_cnt_reg[1]_rep_n_0 | 257 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[0] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[10] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[11] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[1] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[2] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[5] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[6] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[7] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[8] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[9] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_active_reg_rep__7[0] | 256 | LUT5 |
|
||||
| u_matmul_axi_slave/sel0[1] | 259 | FDRE |
|
||||
| u_matmul_axi_slave/b1_b_reg[0][31]_i_8_n_7 | 258 | CARRY4 |
|
||||
| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0 | 258 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9] | 256 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_phase_reg[1]_0[0] | 256 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 |
|
||||
| u_matmul_axi_slave/m_in_b[0][31]_i_1_n_0 | 256 | LUT6 |
|
||||
| u_matmul_axi_slave/m_in_a[3][31]_i_1_n_0 | 256 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 |
|
||||
| u_matmul_axi_slave/w_addr[5] | 246 | FDRE |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT3 |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT2 |
|
||||
| u_matmul_axi_slave/b0_a[6][25]_i_2_n_0 | 242 | LUT2 |
|
||||
| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 239 | LUT3 |
|
||||
| u_matmul_axi_slave/m_in_a[3][30]_i_6_n_0 | 238 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6] | 237 | FDCE |
|
||||
| u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 |
|
||||
| u_cpu/mem_stage/E[0] | 234 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9] | 234 | FDCE |
|
||||
| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 229 | LUT3 |
|
||||
| u_matmul_axi_slave/m_in_b[0][31]_i_7_n_0 | 228 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1] | 227 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[3] | 231 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0 | 224 | LUT4 |
|
||||
@@ -150,72 +113,109 @@ High Fan-out Nets Information
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 219 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[5] | 219 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 216 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 216 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 215 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[2] | 215 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 214 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 214 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4] | 214 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 212 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 212 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 212 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 212 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 212 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 212 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 212 | RAMB36E1 |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 |
|
||||
| u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 |
|
||||
| u_cpu/u_csr/tlbw_r_tlbidx[2] | 210 | FDRE |
|
||||
| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0] | 203 | FDRE |
|
||||
| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[1] | 203 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[6] | 200 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4] | 200 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[3] | 197 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[7] | 207 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1] | 206 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/grp_ptr_r_reg_n_0_[2] | 196 | FDCE |
|
||||
| u_snix_axil_cdma_mux_8ch/ADDRA[0] | 196 | LUT6 |
|
||||
| u_cpu/wb_stage/Q[33] | 194 | FDRE |
|
||||
| u_cpu/wb_stage/Q[34] | 194 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[5] | 194 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[3] | 193 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r_reg[4]_rep_n_0 | 191 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[2] | 187 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[3] | 187 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1] | 187 | FDCE |
|
||||
| u_matmul_axi_slave/current_r_offset[4] | 187 | LUT5 |
|
||||
| u_matmul_axi_slave/s_axi_wready_reg_1 | 181 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg_n_0_[3] | 187 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[2] | 186 | FDCE |
|
||||
| u_cpu/wb_stage/ws_valid_reg_0 | 180 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[3] | 180 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 177 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[0] | 176 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 180 | FDCE |
|
||||
| u_matmul_axi_slave/b0_b_reg[1][30]_i_4_n_7 | 178 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 176 | FDCE |
|
||||
| u_matmul_axi_slave/p_0_in__0 | 176 | LUT4 |
|
||||
| u_matmul_axi_slave/p_0_in__0__0 | 176 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt114_out | 175 | LUT2 |
|
||||
| u_cpu/wb_stage/Q[37] | 173 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[7] | 173 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]_i_4_n_7 | 171 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]_rep__0_n_0 | 172 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[131][11]_i_4_n_0 | 171 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[127]_i_2_n_0 | 169 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[383]_i_2_n_0 | 169 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[639]_i_2_n_0 | 169 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[895]_i_2_n_0 | 169 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 169 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[5] | 166 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r2[3] | 169 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[74][11]_i_4_n_0 | 168 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[6]_0[0] | 168 | CARRY4 |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_0 | 167 | LUT2 |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_1 | 167 | LUT2 |
|
||||
| u_snix_axil_cdma_mux_8ch/ADDRA[0] | 167 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[129][11]_i_3_n_0 | 166 | LUT3 |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__0_n_0 | 165 | FDRE |
|
||||
| u_cpu/wb_stage/Q[32] | 164 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0] | 164 | FDCE |
|
||||
| u_cpu/wb_stage/Q[35] | 163 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg[0]_rep__0_n_0 | 163 | FDCE |
|
||||
| u_cpu/wb_stage/Q[36] | 162 | FDRE |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0 | 161 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1023]_i_2_n_0 | 160 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[255]_i_2_n_0 | 160 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[511]_i_2_n_0 | 160 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[767]_i_2_n_0 | 160 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__12_n_0 | 158 | FDCE |
|
||||
| u_matmul_axi_slave/w_addr_reg[3]_rep__2_0 | 158 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[181][5]_i_3_n_0 | 157 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[6] | 156 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3] | 155 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[6] | 153 | FDCE |
|
||||
| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 153 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[7] | 155 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[3] | 154 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[4] | 154 | FDCE |
|
||||
| u_matmul_axi_slave/w_addr[3] | 153 | FDRE |
|
||||
| u_cpu/axi_bridge/FSM_sequential_write_requst_state_reg[1]_0 | 151 | FDRE |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/num_bytes_comb1 | 150 | CARRY4 |
|
||||
| u_cpu/dcache/awaddr[31]_i_3_n_0 | 148 | LUT2 |
|
||||
| u_cpu/dcache/awaddr[31]_i_4_n_0 | 148 | LUT2 |
|
||||
| u_matmul_axi_slave/s_axi_wready_reg_0 | 148 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1] | 148 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[202][11]_i_3_n_0 | 148 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0] | 147 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__1_n_0 | 146 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep_n_0 | 146 | FDCE |
|
||||
| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 146 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[0] | 145 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_63_n_0 | 144 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6] | 143 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6] | 143 | FDCE |
|
||||
| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0 | 143 | LUT3 |
|
||||
| u_matmul_axi_slave/pipe_cnt[3]_i_4_n_0 | 143 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep_n_0 | 142 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4] | 141 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__10_n_0 | 145 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[2] | 144 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/hek_r[247]_i_3_n_0 | 144 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/hek_r[255]_i_3_n_0 | 144 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__17_n_0 | 143 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[106][11]_i_3_n_0 | 143 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6] | 142 | FDCE |
|
||||
| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[0] | 142 | FDSE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[5] | 141 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[5] | 141 | FDCE |
|
||||
| u_cpu/dcache/write_buffer_state | 140 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_reg_rep__6_n_0 | 140 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4] | 140 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[5] | 140 | FDCE |
|
||||
| u_cpu/u_csr/tlbw_r_tlbidx[0] | 139 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_37_n_0 | 139 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep__3_n_0 | 139 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[7] | 140 | FDCE |
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
|
||||
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:05 2026
|
||||
| Date : Fri Jul 10 04:14:46 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_methodology -file /home/fallensigh/vivado_reports_nodsp/methodology.rpt
|
||||
| Command : report_methodology -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/methodology.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Routed
|
||||
------------------------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Methodology
|
||||
|
||||
@@ -23,13 +23,13 @@ Table of Contents
|
||||
Floorplan: impl_1
|
||||
Design limits: <entire design considered>
|
||||
Max violations: <unlimited>
|
||||
Violations found: 99
|
||||
Violations found: 107
|
||||
+-----------+----------+-------------------------------------------------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+-----------+----------+-------------------------------------------------------------------+------------+
|
||||
| LUTAR-1 | Warning | LUT drives async reset alert | 1 |
|
||||
| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 8 |
|
||||
| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 1 |
|
||||
| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 9 |
|
||||
| SYNTH-16 | Warning | Address collision | 8 |
|
||||
| TIMING-10 | Warning | Missing property on synchronizer | 1 |
|
||||
| TIMING-18 | Warning | Missing input or output delay | 76 |
|
||||
@@ -42,7 +42,7 @@ Table of Contents
|
||||
-----------------
|
||||
LUTAR-1#1 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24584 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24656 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-5#1 Warning
|
||||
@@ -87,7 +87,47 @@ Related violations: <none>
|
||||
|
||||
SYNTH-6#1 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#2 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#3 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#4 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#5 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#6 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#7 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#8 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#9 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-16#1 Warning
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,16 +1,16 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:25 2026
|
||||
| Date : Fri Jul 10 04:15:05 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_power -file /home/fallensigh/vivado_reports_nodsp/power.rpt
|
||||
| Command : report_power -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/power.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Design State : routed
|
||||
| Grade : commercial
|
||||
| Process : typical
|
||||
| Characterization : Production
|
||||
------------------------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Power Report
|
||||
|
||||
@@ -30,14 +30,14 @@ Table of Contents
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
| Total On-Chip Power (W) | 0.549 |
|
||||
| Total On-Chip Power (W) | 0.686 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 0.409 |
|
||||
| Dynamic (W) | 0.545 |
|
||||
| Device Static (W) | 0.141 |
|
||||
| Effective TJA (C/W) | 1.9 |
|
||||
| Max Ambient (C) | 84.0 |
|
||||
| Junction Temperature (C) | 26.0 |
|
||||
| Max Ambient (C) | 83.7 |
|
||||
| Junction Temperature (C) | 26.3 |
|
||||
| Confidence Level | Low |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
@@ -52,22 +52,21 @@ Table of Contents
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| Clocks | 0.042 | 7 | --- | --- |
|
||||
| Slice Logic | 0.069 | 120086 | --- | --- |
|
||||
| LUT as Logic | 0.064 | 63754 | 133800 | 47.65 |
|
||||
| CARRY4 | 0.002 | 2859 | 33450 | 8.55 |
|
||||
| LUT as Distributed RAM | <0.001 | 740 | 46200 | 1.60 |
|
||||
| Register | <0.001 | 39931 | 267600 | 14.92 |
|
||||
| Clocks | 0.056 | 6 | --- | --- |
|
||||
| Slice Logic | 0.109 | 133224 | --- | --- |
|
||||
| LUT as Logic | 0.102 | 75460 | 133800 | 56.40 |
|
||||
| CARRY4 | 0.003 | 3546 | 33450 | 10.60 |
|
||||
| LUT as Distributed RAM | 0.002 | 628 | 46200 | 1.36 |
|
||||
| Register | 0.001 | 39690 | 267600 | 14.83 |
|
||||
| LUT as Shift Register | <0.001 | 1175 | 46200 | 2.54 |
|
||||
| F7/F8 Muxes | <0.001 | 6036 | 133800 | 4.51 |
|
||||
| Others | 0.000 | 318 | --- | --- |
|
||||
| Signals | 0.115 | 85084 | --- | --- |
|
||||
| Block RAM | 0.019 | 23.5 | 365 | 6.44 |
|
||||
| PLL | 0.132 | 1 | 10 | 10.00 |
|
||||
| DSPs | 0.009 | 16 | 740 | 2.16 |
|
||||
| I/O | 0.023 | 202 | 400 | 50.50 |
|
||||
| F7/F8 Muxes | <0.001 | 6085 | 133800 | 4.55 |
|
||||
| Others | 0.000 | 289 | --- | --- |
|
||||
| Signals | 0.194 | 93202 | --- | --- |
|
||||
| Block RAM | 0.019 | 25.5 | 365 | 6.99 |
|
||||
| PLL | 0.137 | 1 | 10 | 10.00 |
|
||||
| I/O | 0.029 | 202 | 400 | 50.50 |
|
||||
| Static Power | 0.141 | | | |
|
||||
| Total | 0.549 | | | |
|
||||
| Total | 0.686 | | | |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
@@ -77,9 +76,9 @@ Table of Contents
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Vccint | 1.000 | 0.294 | 0.262 | 0.032 |
|
||||
| Vccaux | 1.800 | 0.099 | 0.069 | 0.031 |
|
||||
| Vcco33 | 3.300 | 0.011 | 0.006 | 0.005 |
|
||||
| Vccint | 1.000 | 0.423 | 0.391 | 0.032 |
|
||||
| Vccaux | 1.800 | 0.101 | 0.070 | 0.031 |
|
||||
| Vcco33 | 3.300 | 0.013 | 0.008 | 0.005 |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
|
||||
@@ -130,15 +129,14 @@ Table of Contents
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
+-------------------+------------------------------------------+-----------------+
|
||||
+------------------+-----------------------------------------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+-------------------+------------------------------------------+-----------------+
|
||||
+------------------+-----------------------------------------+-----------------+
|
||||
| clk | clk | 20.0 |
|
||||
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
|
||||
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 |
|
||||
| mlkem_clk_clk_pll | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 40.0 |
|
||||
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
|
||||
+-------------------+------------------------------------------+-----------------+
|
||||
+------------------+-----------------------------------------+-----------------+
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
@@ -150,29 +148,32 @@ Table of Contents
|
||||
+----------------------------+-----------+
|
||||
| Name | Power (W) |
|
||||
+----------------------------+-----------+
|
||||
| soc_top | 0.409 |
|
||||
| pll_clk.u_clk_pll | 0.133 |
|
||||
| inst | 0.133 |
|
||||
| u_Axi_CDC | 0.002 |
|
||||
| u_axi_uart_controller | 0.001 |
|
||||
| uart0 | 0.001 |
|
||||
| regs | 0.001 |
|
||||
| u_cdma_matmul_bridge | 0.001 |
|
||||
| u_cpu | 0.018 |
|
||||
| soc_top | 0.545 |
|
||||
| pll_clk.u_clk_pll | 0.138 |
|
||||
| inst | 0.138 |
|
||||
| u_Axi_CDC | 0.003 |
|
||||
| u_axi_uart_controller | 0.002 |
|
||||
| u_cpu | 0.025 |
|
||||
| addr_trans | 0.002 |
|
||||
| tlb_entry | 0.002 |
|
||||
| btb | 0.002 |
|
||||
| dcache | 0.004 |
|
||||
| btb | 0.003 |
|
||||
| dcache | 0.006 |
|
||||
| icache | 0.005 |
|
||||
| u_csr | 0.002 |
|
||||
| u_fft_mlkem_axi_slave | 0.148 |
|
||||
| u_fft_controller | 0.032 |
|
||||
| u_FFT | 0.029 |
|
||||
| u_mlkem_axi_cdc | 0.002 |
|
||||
| u_mlkem_axi_slave | 0.115 |
|
||||
| u_mlkem | 0.113 |
|
||||
| u_matmul_axi_slave | 0.065 |
|
||||
| u_snix_axil_cdma_mux_8ch | 0.009 |
|
||||
| u_csr | 0.001 |
|
||||
| u_mul | 0.004 |
|
||||
| u_fft_mlkem_axi_slave | 0.251 |
|
||||
| u_fft_controller | 0.030 |
|
||||
| u_FFT | 0.027 |
|
||||
| u_out0 | 0.001 |
|
||||
| u_out1 | 0.001 |
|
||||
| u_mlkem_axi_slave | 0.221 |
|
||||
| u_mlkem | 0.218 |
|
||||
| u_matmul_axi_slave | 0.081 |
|
||||
| mult_inst[0].u_mult | 0.003 |
|
||||
| mult_inst[1].u_mult | 0.002 |
|
||||
| mult_inst[2].u_mult | 0.002 |
|
||||
| mult_inst[3].u_mult | 0.002 |
|
||||
| u_snix_axil_cdma_mux_8ch | 0.008 |
|
||||
| u_core_engine | 0.004 |
|
||||
| axis_fifo_u0 | 0.003 |
|
||||
+----------------------------+-----------+
|
||||
|
||||
@@ -1,12 +1,12 @@
|
||||
Design Route Status
|
||||
: # nets :
|
||||
------------------------------------------- : ----------- :
|
||||
# of logical nets.......................... : 128919 :
|
||||
# of nets not needing routing.......... : 43824 :
|
||||
# of internally routed nets........ : 43359 :
|
||||
# of nets with no loads............ : 465 :
|
||||
# of routable nets..................... : 85095 :
|
||||
# of fully routed nets............. : 85095 :
|
||||
# of logical nets.......................... : 144034 :
|
||||
# of nets not needing routing.......... : 50823 :
|
||||
# of internally routed nets........ : 50442 :
|
||||
# of nets with no loads............ : 381 :
|
||||
# of routable nets..................... : 93211 :
|
||||
# of fully routed nets............. : 93211 :
|
||||
# of nets with routing errors.......... : 0 :
|
||||
------------------------------------------- : ----------- :
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:05 2026
|
||||
| Date : Fri Jul 10 04:14:47 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -file /home/fallensigh/vivado_reports_nodsp/utilization.rpt
|
||||
| Command : report_utilization -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/utilization.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Routed
|
||||
------------------------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
@@ -31,16 +31,16 @@ Table of Contents
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
| Slice LUTs | 60995 | 0 | 133800 | 45.59 |
|
||||
| LUT as Logic | 59140 | 0 | 133800 | 44.20 |
|
||||
| LUT as Memory | 1855 | 0 | 46200 | 4.02 |
|
||||
| LUT as Distributed RAM | 740 | 0 | | |
|
||||
| Slice LUTs | 71196 | 0 | 133800 | 53.21 |
|
||||
| LUT as Logic | 69453 | 0 | 133800 | 51.91 |
|
||||
| LUT as Memory | 1743 | 0 | 46200 | 3.77 |
|
||||
| LUT as Distributed RAM | 628 | 0 | | |
|
||||
| LUT as Shift Register | 1115 | 0 | | |
|
||||
| Slice Registers | 39931 | 0 | 267600 | 14.92 |
|
||||
| Register as Flip Flop | 39931 | 0 | 267600 | 14.92 |
|
||||
| Slice Registers | 39690 | 0 | 267600 | 14.83 |
|
||||
| Register as Flip Flop | 39690 | 0 | 267600 | 14.83 |
|
||||
| Register as Latch | 0 | 0 | 267600 | 0.00 |
|
||||
| F7 Muxes | 4480 | 0 | 66900 | 6.70 |
|
||||
| F8 Muxes | 1556 | 0 | 33450 | 4.65 |
|
||||
| F7 Muxes | 4565 | 0 | 66900 | 6.82 |
|
||||
| F8 Muxes | 1520 | 0 | 33450 | 4.54 |
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
|
||||
|
||||
@@ -57,9 +57,9 @@ Table of Contents
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 24 | Yes | - | Set |
|
||||
| 26637 | Yes | - | Reset |
|
||||
| 26562 | Yes | - | Reset |
|
||||
| 139 | Yes | Set | - |
|
||||
| 13131 | Yes | Reset | - |
|
||||
| 12965 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
@@ -69,28 +69,28 @@ Table of Contents
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
| Slice | 20066 | 0 | 33450 | 59.99 |
|
||||
| SLICEL | 13210 | 0 | | |
|
||||
| SLICEM | 6856 | 0 | | |
|
||||
| LUT as Logic | 59140 | 0 | 133800 | 44.20 |
|
||||
| Slice | 21289 | 0 | 33450 | 63.64 |
|
||||
| SLICEL | 13965 | 0 | | |
|
||||
| SLICEM | 7324 | 0 | | |
|
||||
| LUT as Logic | 69453 | 0 | 133800 | 51.91 |
|
||||
| using O5 output only | 2 | | | |
|
||||
| using O6 output only | 49931 | | | |
|
||||
| using O5 and O6 | 9207 | | | |
|
||||
| LUT as Memory | 1855 | 0 | 46200 | 4.02 |
|
||||
| LUT as Distributed RAM | 740 | 0 | | |
|
||||
| using O6 output only | 57661 | | | |
|
||||
| using O5 and O6 | 11790 | | | |
|
||||
| LUT as Memory | 1743 | 0 | 46200 | 3.77 |
|
||||
| LUT as Distributed RAM | 628 | 0 | | |
|
||||
| using O5 output only | 0 | | | |
|
||||
| using O6 output only | 60 | | | |
|
||||
| using O5 and O6 | 680 | | | |
|
||||
| using O5 and O6 | 568 | | | |
|
||||
| LUT as Shift Register | 1115 | 0 | | |
|
||||
| using O5 output only | 47 | | | |
|
||||
| using O6 output only | 1008 | | | |
|
||||
| using O5 and O6 | 60 | | | |
|
||||
| Slice Registers | 39931 | 0 | 267600 | 14.92 |
|
||||
| Register driven from within the Slice | 20433 | | | |
|
||||
| Register driven from outside the Slice | 19498 | | | |
|
||||
| LUT in front of the register is unused | 10788 | | | |
|
||||
| LUT in front of the register is used | 8710 | | | |
|
||||
| Unique Control Sets | 1304 | | 33450 | 3.90 |
|
||||
| Slice Registers | 39690 | 0 | 267600 | 14.83 |
|
||||
| Register driven from within the Slice | 24917 | | | |
|
||||
| Register driven from outside the Slice | 14773 | | | |
|
||||
| LUT in front of the register is unused | 6243 | | | |
|
||||
| LUT in front of the register is used | 8530 | | | |
|
||||
| Unique Control Sets | 1278 | | 33450 | 3.82 |
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
@@ -101,9 +101,9 @@ Table of Contents
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 23.5 | 0 | 365 | 6.44 |
|
||||
| RAMB36/FIFO* | 8 | 0 | 365 | 2.19 |
|
||||
| RAMB36E1 only | 8 | | | |
|
||||
| Block RAM Tile | 25.5 | 0 | 365 | 6.99 |
|
||||
| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 |
|
||||
| RAMB36E1 only | 10 | | | |
|
||||
| RAMB18 | 31 | 0 | 730 | 4.25 |
|
||||
| RAMB18E1 only | 31 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
@@ -113,12 +113,11 @@ Table of Contents
|
||||
4. DSP
|
||||
------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| DSPs | 16 | 0 | 740 | 2.16 |
|
||||
| DSP48E1 only | 16 | | | |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 740 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. IO and GT Specific
|
||||
@@ -154,7 +153,7 @@ Table of Contents
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 4 | 0 | 32 | 12.50 |
|
||||
| BUFGCTRL | 3 | 0 | 32 | 9.38 |
|
||||
| BUFIO | 0 | 0 | 40 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
|
||||
@@ -188,20 +187,20 @@ Table of Contents
|
||||
+-----------+-------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+-----------+-------+---------------------+
|
||||
| LUT6 | 35413 | LUT |
|
||||
| FDCE | 26637 | Flop & Latch |
|
||||
| FDRE | 13131 | Flop & Latch |
|
||||
| LUT3 | 9384 | LUT |
|
||||
| LUT5 | 8477 | LUT |
|
||||
| LUT4 | 7294 | LUT |
|
||||
| LUT2 | 6978 | LUT |
|
||||
| MUXF7 | 4480 | MuxFx |
|
||||
| CARRY4 | 2859 | CarryLogic |
|
||||
| MUXF8 | 1556 | MuxFx |
|
||||
| RAMD32 | 1060 | Distributed Memory |
|
||||
| LUT6 | 37981 | LUT |
|
||||
| FDCE | 26562 | Flop & Latch |
|
||||
| FDRE | 12965 | Flop & Latch |
|
||||
| LUT5 | 12781 | LUT |
|
||||
| LUT4 | 10316 | LUT |
|
||||
| LUT3 | 10135 | LUT |
|
||||
| LUT2 | 9228 | LUT |
|
||||
| MUXF7 | 4565 | MuxFx |
|
||||
| CARRY4 | 3546 | CarryLogic |
|
||||
| MUXF8 | 1520 | MuxFx |
|
||||
| SRLC32E | 992 | Distributed Memory |
|
||||
| LUT1 | 801 | LUT |
|
||||
| RAMS32 | 328 | Distributed Memory |
|
||||
| RAMD32 | 892 | Distributed Memory |
|
||||
| LUT1 | 802 | LUT |
|
||||
| RAMS32 | 272 | Distributed Memory |
|
||||
| SRL16E | 183 | Distributed Memory |
|
||||
| FDSE | 139 | Flop & Latch |
|
||||
| IBUF | 104 | IO |
|
||||
@@ -210,9 +209,8 @@ Table of Contents
|
||||
| RAMD64E | 32 | Distributed Memory |
|
||||
| RAMB18E1 | 31 | Block Memory |
|
||||
| FDPE | 24 | Flop & Latch |
|
||||
| DSP48E1 | 16 | Block Arithmetic |
|
||||
| RAMB36E1 | 8 | Block Memory |
|
||||
| BUFG | 4 | Clock |
|
||||
| RAMB36E1 | 10 | Block Memory |
|
||||
| BUFG | 3 | Clock |
|
||||
| PLLE2_ADV | 1 | Clock |
|
||||
+-----------+-------+---------------------+
|
||||
|
||||
|
||||
@@ -1,13 +1,13 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:06 2026
|
||||
| Date : Fri Jul 10 04:14:48 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -hierarchical -file /home/fallensigh/vivado_reports_nodsp/utilization_hier.rpt
|
||||
| Command : report_utilization -hierarchical -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/utilization_hier.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Routed
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
@@ -21,255 +21,232 @@ Table of Contents
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
| soc_top | (top) | 60995 | 59140 | 740 | 1115 | 39931 | 8 | 31 | 16 |
|
||||
| (soc_top) | (top) | 878 | 822 | 56 | 0 | 4 | 0 | 0 | 0 |
|
||||
| soc_top | (top) | 71196 | 69453 | 628 | 1115 | 39690 | 10 | 31 | 0 |
|
||||
| (soc_top) | (top) | 868 | 812 | 56 | 0 | 4 | 0 | 0 | 0 |
|
||||
| pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| inst | clk_pll__clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| inst | clk_pll_clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_mlkem | rst_sync_0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_sys | rst_sync_1 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 459 | 459 | 0 | 0 | 151 | 0 | 0 | 0 |
|
||||
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 6 | 6 | 0 | 0 | 24 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_82 | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_65 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_81 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_66 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_80 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_67 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_79 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_sys | rst_sync_0 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 357 | 357 | 0 | 0 | 151 | 0 | 0 | 0 |
|
||||
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 19 | 19 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_64 | 19 | 19 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_47 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_63 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_48 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_62 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_49 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_61 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 30 | 30 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_76 | 27 | 27 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_77 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_78 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_58 | 24 | 24 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_59 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_60 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_73 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_74 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_75 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_55 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_56 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_57 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 26 | 26 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_70 | 20 | 20 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_71 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_72 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 23 | 23 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_52 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_53 | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_54 | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 27 | 27 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 96 | 96 | 0 | 0 | 25 | 0 | 0 | 0 |
|
||||
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 75 | 75 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4ReadOnlyErrorSlave_1_69 | 21 | 21 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 40 | 40 | 0 | 0 | 18 | 0 | 0 | 0 |
|
||||
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 20 | 20 | 0 | 0 | 16 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1_68 | 21 | 21 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 133 | 133 | 0 | 0 | 17 | 0 | 0 | 0 |
|
||||
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 118 | 118 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7 | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 89 | 89 | 0 | 0 | 25 | 0 | 0 | 0 |
|
||||
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 73 | 73 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4ReadOnlyErrorSlave_1_51 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 |
|
||||
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1_50 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 55 | 55 | 0 | 0 | 17 | 0 | 0 | 0 |
|
||||
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 41 | 41 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
|
||||
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 30 | 30 | 0 | 0 | 14 | 0 | 0 | 0 |
|
||||
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 23 | 23 | 0 | 0 | 14 | 0 | 0 | 0 |
|
||||
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 18 | 18 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_Axi_CDC | Axi_CDC | 410 | 282 | 128 | 0 | 317 | 0 | 0 | 0 |
|
||||
| arFifo | StreamFifoCC_3_48 | 181 | 145 | 36 | 0 | 77 | 0 | 0 | 0 |
|
||||
| (arFifo) | StreamFifoCC_3_48 | 176 | 140 | 36 | 0 | 65 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_63 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_64 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| awFifo | StreamFifoCC_49 | 103 | 67 | 36 | 0 | 79 | 0 | 0 | 0 |
|
||||
| (awFifo) | StreamFifoCC_49 | 99 | 63 | 36 | 0 | 65 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_10_60 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_61 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_62 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| bFifo | StreamFifoCC_2_50 | 15 | 15 | 0 | 0 | 26 | 0 | 0 | 0 |
|
||||
| (bFifo) | StreamFifoCC_2_50 | 8 | 8 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_5_57 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_4_58 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_6_59 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| rFifo | StreamFifoCC_4_51 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 |
|
||||
| (rFifo) | StreamFifoCC_4_51 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_55 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_1_56 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| wFifo | StreamFifoCC_1_52 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 |
|
||||
| (wFifo) | StreamFifoCC_1_52 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_7_53 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_8_54 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_axi_axil_adapter | axi_axil_adapter | 1073 | 1073 | 0 | 0 | 173 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 498 | 498 | 0 | 0 | 85 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 575 | 575 | 0 | 0 | 88 | 0 | 0 | 0 |
|
||||
| u_axi_dvi | axi_dvi | 283 | 283 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| u_axi_ram | axi_wrap_ram_sp_external | 350 | 350 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| u_axi_sram_sp | axi2sram_sp_external | 350 | 350 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_Axi_CDC | Axi_CDC | 407 | 279 | 128 | 0 | 309 | 0 | 0 | 0 |
|
||||
| arFifo | StreamFifoCC_3 | 180 | 144 | 36 | 0 | 73 | 0 | 0 | 0 |
|
||||
| (arFifo) | StreamFifoCC_3 | 174 | 138 | 36 | 0 | 61 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_45 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_46 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| awFifo | StreamFifoCC | 101 | 65 | 36 | 0 | 75 | 0 | 0 | 0 |
|
||||
| (awFifo) | StreamFifoCC | 94 | 58 | 36 | 0 | 61 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| bFifo | StreamFifoCC_2 | 14 | 14 | 0 | 0 | 26 | 0 | 0 | 0 |
|
||||
| (bFifo) | StreamFifoCC_2 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_4 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_6 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| rFifo | StreamFifoCC_4 | 46 | 18 | 28 | 0 | 66 | 0 | 0 | 0 |
|
||||
| (rFifo) | StreamFifoCC_4 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_1 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| wFifo | StreamFifoCC_1 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 |
|
||||
| (wFifo) | StreamFifoCC_1 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_8 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_axi_axil_adapter | axi_axil_adapter | 1338 | 1338 | 0 | 0 | 161 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 635 | 635 | 0 | 0 | 81 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 703 | 703 | 0 | 0 | 80 | 0 | 0 | 0 |
|
||||
| u_axi_dvi | axi_dvi | 284 | 284 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| u_axi_ram | axi_wrap_ram_sp_external | 354 | 354 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| u_axi_sram_sp | axi2sram_sp_external | 354 | 354 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| u_axi_uart_controller | axi_uart_controller | 683 | 667 | 16 | 0 | 457 | 0 | 0 | 0 |
|
||||
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 251 | 251 | 0 | 0 | 120 | 0 | 0 | 0 |
|
||||
| uart0 | UART_TOP | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| regs | uart_regs | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| (regs) | uart_regs | 119 | 119 | 0 | 0 | 155 | 0 | 0 | 0 |
|
||||
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 250 | 250 | 0 | 0 | 120 | 0 | 0 | 0 |
|
||||
| uart0 | UART_TOP | 433 | 417 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| regs | uart_regs | 433 | 417 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| (regs) | uart_regs | 118 | 118 | 0 | 0 | 155 | 0 | 0 | 0 |
|
||||
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 |
|
||||
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
|
||||
| fifo_rx | uart_rfifo | 161 | 153 | 8 | 0 | 70 | 0 | 0 | 0 |
|
||||
| (fifo_rx) | uart_rfifo | 143 | 143 | 0 | 0 | 62 | 0 | 0 | 0 |
|
||||
| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| rfifo | raminfr_44 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 |
|
||||
| (transmitter) | uart_transmitter | 41 | 41 | 0 | 0 | 35 | 0 | 0 | 0 |
|
||||
| fifo_tx | uart_tfifo | 43 | 35 | 8 | 0 | 21 | 0 | 0 | 0 |
|
||||
| (fifo_tx) | uart_tfifo | 24 | 24 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_cdma_matmul_bridge | cdma_matmul_bridge | 251 | 251 | 0 | 0 | 578 | 0 | 0 | 0 |
|
||||
| u_cdma_matmul_bridge | cdma_matmul_bridge | 247 | 247 | 0 | 0 | 578 | 0 | 0 | 0 |
|
||||
| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 |
|
||||
| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 |
|
||||
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
|
||||
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
|
||||
| u_cpu | core_top | 8551 | 8299 | 252 | 0 | 5591 | 0 | 20 | 0 |
|
||||
| u_cpu | core_top | 8553 | 8301 | 252 | 0 | 5591 | 0 | 20 | 0 |
|
||||
| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 |
|
||||
| addr_trans | addr_trans | 2247 | 2107 | 140 | 0 | 1244 | 0 | 0 | 0 |
|
||||
| addr_trans | addr_trans | 2249 | 2109 | 140 | 0 | 1244 | 0 | 0 | 0 |
|
||||
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
|
||||
| tlb_entry | tlb_entry | 2247 | 2107 | 140 | 0 | 1204 | 0 | 0 | 0 |
|
||||
| axi_bridge | axi_bridge | 40 | 40 | 0 | 0 | 214 | 0 | 0 | 0 |
|
||||
| tlb_entry | tlb_entry | 2249 | 2109 | 140 | 0 | 1204 | 0 | 0 | 0 |
|
||||
| axi_bridge | axi_bridge | 39 | 39 | 0 | 0 | 214 | 0 | 0 | 0 |
|
||||
| btb | btb | 1046 | 966 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
||||
| (btb) | btb | 1044 | 964 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
||||
| (btb) | btb | 1043 | 963 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
||||
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| dcache | dcache | 552 | 520 | 32 | 0 | 146 | 0 | 10 | 0 |
|
||||
| dcache | dcache | 553 | 521 | 32 | 0 | 146 | 0 | 10 | 0 |
|
||||
| (dcache) | dcache | 87 | 55 | 32 | 0 | 138 | 0 | 0 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_46 | 41 | 41 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| exe_stage | exe_stage | 663 | 663 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| (exe_stage) | exe_stage | 632 | 632 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_33 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_34 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_35 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_36 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_39 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_40 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| lfsr | lfsr_41 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[0].u | tagv_sram_42 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_43 | 41 | 41 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| exe_stage | exe_stage | 664 | 664 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| (exe_stage) | exe_stage | 633 | 633 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| icache | icache | 235 | 235 | 0 | 0 | 55 | 0 | 10 | 0 |
|
||||
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_25 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_26 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_27 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_29 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_30 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_31 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_35 | 87 | 87 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| id_stage | id_stage | 1054 | 1054 | 0 | 0 | 108 | 0 | 0 | 0 |
|
||||
| if_stage | if_stage | 135 | 135 | 0 | 0 | 173 | 0 | 0 | 0 |
|
||||
| mem_stage | mem_stage | 116 | 116 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_32 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| id_stage | id_stage | 1050 | 1050 | 0 | 0 | 108 | 0 | 0 | 0 |
|
||||
| if_stage | if_stage | 134 | 134 | 0 | 0 | 173 | 0 | 0 | 0 |
|
||||
| mem_stage | mem_stage | 117 | 117 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 |
|
||||
| u_div | div | 142 | 142 | 0 | 0 | 107 | 0 | 0 | 0 |
|
||||
| u_mul | mul | 936 | 936 | 0 | 0 | 592 | 0 | 0 | 0 |
|
||||
| wb_stage | wb_stage | 680 | 680 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 36148 | 34927 | 112 | 1109 | 27165 | 8 | 10 | 16 |
|
||||
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| u_fft_controller | fft_controller | 2646 | 1606 | 0 | 1040 | 1083 | 6 | 4 | 16 |
|
||||
| (u_fft_controller) | fft_controller | 123 | 123 | 0 | 0 | 100 | 0 | 0 | 0 |
|
||||
| u_FFT | FFT | 2496 | 1456 | 0 | 1040 | 983 | 6 | 0 | 16 |
|
||||
| SU1 | SdfUnit | 1071 | 303 | 0 | 768 | 197 | 2 | 0 | 4 |
|
||||
| (SU1) | SdfUnit | 205 | 205 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_25 | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer | 562 | 50 | 0 | 512 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized0 | 256 | 0 | 0 | 256 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| TW | Twiddle_27 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU2 | SdfUnit__parameterized0 | 492 | 300 | 0 | 192 | 197 | 2 | 0 | 4 |
|
||||
| (SU2) | SdfUnit__parameterized0 | 73 | 73 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_mul | mul | 934 | 934 | 0 | 0 | 592 | 0 | 0 | 0 |
|
||||
| wb_stage | wb_stage | 681 | 681 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 45975 | 44866 | 0 | 1109 | 26955 | 10 | 10 | 0 |
|
||||
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 |
|
||||
| u_fft_controller | fft_controller | 6949 | 5909 | 0 | 1040 | 1083 | 8 | 4 | 0 |
|
||||
| (u_fft_controller) | fft_controller | 118 | 118 | 0 | 0 | 100 | 0 | 0 | 0 |
|
||||
| u_FFT | FFT | 6783 | 5743 | 0 | 1040 | 983 | 8 | 0 | 0 |
|
||||
| SU1 | SdfUnit | 2145 | 1377 | 0 | 768 | 197 | 2 | 0 | 0 |
|
||||
| (SU1) | SdfUnit | 39 | 39 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_21 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_22 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer | 624 | 112 | 0 | 512 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized0 | 320 | 64 | 0 | 256 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_23 | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle_24 | 543 | 543 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU2 | SdfUnit__parameterized0 | 1566 | 1374 | 0 | 192 | 197 | 2 | 0 | 0 |
|
||||
| (SU2) | SdfUnit__parameterized0 | 38 | 38 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_17 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_18 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_22 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| TW | Twiddle_23 | 3 | 3 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU3 | SdfUnit__parameterized1 | 346 | 298 | 0 | 48 | 197 | 0 | 0 | 4 |
|
||||
| (SU3) | SdfUnit__parameterized1 | 74 | 74 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_17 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| MU | Multiply_19 | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle_20 | 541 | 541 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU3 | SdfUnit__parameterized1 | 1416 | 1368 | 0 | 48 | 197 | 2 | 0 | 0 |
|
||||
| (SU3) | SdfUnit__parameterized1 | 35 | 35 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_13 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_14 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized4 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_19 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| SU4 | SdfUnit__parameterized2 | 327 | 295 | 0 | 32 | 197 | 2 | 0 | 4 |
|
||||
| (SU4) | SdfUnit__parameterized2 | 69 | 69 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_15 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| MU | Multiply_15 | 610 | 610 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle_16 | 539 | 539 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU4 | SdfUnit__parameterized2 | 1398 | 1366 | 0 | 32 | 197 | 2 | 0 | 0 |
|
||||
| (SU4) | SdfUnit__parameterized2 | 34 | 34 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_11 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_12 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized5 | 128 | 112 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized6 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| TW | Twiddle | 2 | 2 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU5 | SdfUnit__parameterized3 | 260 | 260 | 0 | 0 | 195 | 0 | 0 | 0 |
|
||||
| (SU5) | SdfUnit__parameterized3 | 68 | 68 | 0 | 0 | 99 | 0 | 0 | 0 |
|
||||
| MU | Multiply | 612 | 612 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| TW | Twiddle | 536 | 536 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU5 | SdfUnit__parameterized3 | 258 | 258 | 0 | 0 | 195 | 0 | 0 | 0 |
|
||||
| (SU5) | SdfUnit__parameterized3 | 34 | 34 | 0 | 0 | 99 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
|
||||
| u_in0 | my_bram0 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_in1 | my_bram0_12 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out0 | my_bram0_13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out1 | my_bram0_14 | 25 | 25 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_mlkem_axi_cdc | Axi_CDC_5 | 421 | 309 | 112 | 0 | 272 | 0 | 0 | 0 |
|
||||
| arFifo | StreamFifoCC_3 | 53 | 25 | 28 | 0 | 55 | 0 | 0 | 0 |
|
||||
| (arFifo) | StreamFifoCC_3 | 44 | 16 | 28 | 0 | 43 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_10 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| awFifo | StreamFifoCC | 40 | 16 | 24 | 0 | 49 | 0 | 0 | 0 |
|
||||
| (awFifo) | StreamFifoCC | 31 | 7 | 24 | 0 | 35 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| bFifo | StreamFifoCC_2 | 18 | 14 | 4 | 0 | 27 | 0 | 0 | 0 |
|
||||
| (bFifo) | StreamFifoCC_2 | 11 | 7 | 4 | 0 | 13 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_4 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_6 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| rFifo | StreamFifoCC_4 | 57 | 29 | 28 | 0 | 72 | 0 | 0 | 0 |
|
||||
| (rFifo) | StreamFifoCC_4 | 49 | 21 | 28 | 0 | 56 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_1 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| wFifo | StreamFifoCC_1 | 253 | 225 | 28 | 0 | 69 | 0 | 0 | 0 |
|
||||
| (wFifo) | StreamFifoCC_1 | 248 | 220 | 28 | 0 | 53 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_8 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_mlkem_axi_slave | mlkem_axi_slave | 33082 | 33013 | 0 | 69 | 25804 | 2 | 6 | 0 |
|
||||
| (u_mlkem_axi_slave) | mlkem_axi_slave | 1202 | 1202 | 0 | 0 | 1068 | 0 | 0 | 0 |
|
||||
| u_mlkem | mlkem_top | 31884 | 31815 | 0 | 69 | 24736 | 2 | 6 | 0 |
|
||||
| (u_mlkem) | mlkem_top | 2738 | 2738 | 0 | 0 | 4960 | 0 | 0 | 0 |
|
||||
| u_bank_a | sd_bram__parameterized0 | 50 | 50 | 0 | 0 | 0 | 1 | 1 | 0 |
|
||||
| u_in1 | my_bram0_8 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out0 | my_bram0_9 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out1 | my_bram0_10 | 45 | 45 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_mlkem_axi_slave | mlkem_axi_slave | 39029 | 38960 | 0 | 69 | 25868 | 2 | 6 | 0 |
|
||||
| (u_mlkem_axi_slave) | mlkem_axi_slave | 1332 | 1332 | 0 | 0 | 1060 | 0 | 0 | 0 |
|
||||
| u_mlkem | mlkem_top | 37700 | 37631 | 0 | 69 | 24808 | 2 | 6 | 0 |
|
||||
| (u_mlkem) | mlkem_top | 2754 | 2754 | 0 | 0 | 4949 | 0 | 0 | 0 |
|
||||
| u_bank_a | sd_bram__parameterized0 | 51 | 51 | 0 | 0 | 0 | 1 | 1 | 0 |
|
||||
| u_bank_se | sd_bram__parameterized1 | 70 | 70 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| u_bank_t | sd_bram__parameterized2 | 654 | 654 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_bank_t | sd_bram__parameterized2 | 683 | 683 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_c_in_bram | sd_bram | 1312 | 1312 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_cbd | sample_cbd_sync_shared | 2741 | 2741 | 0 | 0 | 3186 | 0 | 0 | 0 |
|
||||
| u_comp | comp_decomp_sync | 467 | 466 | 0 | 1 | 323 | 0 | 0 | 0 |
|
||||
| u_ct_bram | sd_bram_6 | 13 | 13 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_dkp_bram | sd_bram_7 | 82 | 82 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_ek_bram | sd_bram_8 | 2121 | 2121 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_keccak | keccak_core | 5274 | 5274 | 0 | 0 | 1606 | 0 | 0 | 0 |
|
||||
| u_ntt | ntt_core | 8625 | 8582 | 0 | 43 | 3861 | 0 | 0 | 0 |
|
||||
| (u_ntt) | ntt_core | 6101 | 6085 | 0 | 16 | 3358 | 0 | 0 | 0 |
|
||||
| u_bf | butterfly_unit_pipe | 2260 | 2234 | 0 | 26 | 286 | 0 | 0 | 0 |
|
||||
| (u_bf) | butterfly_unit_pipe | 69 | 44 | 0 | 25 | 75 | 0 | 0 | 0 |
|
||||
| u_barrett | barrett_mul_pipe_9 | 2192 | 2191 | 0 | 1 | 211 | 0 | 0 | 0 |
|
||||
| u_scl | barrett_mul_pipe | 265 | 264 | 0 | 1 | 217 | 0 | 0 | 0 |
|
||||
| u_pmul | poly_mul_sync | 3881 | 3856 | 0 | 25 | 6743 | 0 | 0 | 0 |
|
||||
| (u_pmul) | poly_mul_sync | 2434 | 2434 | 0 | 0 | 6280 | 0 | 0 | 0 |
|
||||
| u_cbd | sample_cbd_sync_shared | 2753 | 2753 | 0 | 0 | 3186 | 0 | 0 | 0 |
|
||||
| u_comp | comp_decomp_sync | 465 | 464 | 0 | 1 | 323 | 0 | 0 | 0 |
|
||||
| u_ct_bram | sd_bram_4 | 12 | 12 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_dkp_bram | sd_bram_5 | 82 | 82 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_ek_bram | sd_bram_6 | 2006 | 2006 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_keccak | keccak_core | 5271 | 5271 | 0 | 0 | 1606 | 0 | 0 | 0 |
|
||||
| u_ntt | ntt_core | 9893 | 9850 | 0 | 43 | 3869 | 0 | 0 | 0 |
|
||||
| (u_ntt) | ntt_core | 7376 | 7360 | 0 | 16 | 3366 | 0 | 0 | 0 |
|
||||
| u_bf | butterfly_unit_pipe | 2256 | 2230 | 0 | 26 | 286 | 0 | 0 | 0 |
|
||||
| (u_bf) | butterfly_unit_pipe | 58 | 33 | 0 | 25 | 75 | 0 | 0 | 0 |
|
||||
| u_barrett | barrett_mul_pipe_7 | 2198 | 2197 | 0 | 1 | 211 | 0 | 0 | 0 |
|
||||
| u_scl | barrett_mul_pipe | 263 | 262 | 0 | 1 | 217 | 0 | 0 | 0 |
|
||||
| u_pmul | poly_mul_sync | 8281 | 8256 | 0 | 25 | 6818 | 0 | 0 | 0 |
|
||||
| (u_pmul) | poly_mul_sync | 6834 | 6834 | 0 | 0 | 6355 | 0 | 0 | 0 |
|
||||
| u_bc | basecase_mul_pipe | 1447 | 1422 | 0 | 25 | 463 | 0 | 0 | 0 |
|
||||
| u_sha3 | sha3_top_shared | 1766 | 1766 | 0 | 0 | 2388 | 0 | 0 | 0 |
|
||||
| u_snt | sample_ntt_sync_shared | 2109 | 2109 | 0 | 0 | 1669 | 0 | 0 | 0 |
|
||||
| u_matmul_axi_slave | matmul_axi_slave | 9758 | 9576 | 176 | 6 | 3248 | 0 | 0 | 0 |
|
||||
| (u_matmul_axi_slave) | matmul_axi_slave | 5637 | 5455 | 176 | 6 | 2480 | 0 | 0 | 0 |
|
||||
| mult_inst[0].u_mult | pipelined_mult_32x32 | 1063 | 1063 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[1].u_mult | pipelined_mult_32x32_2 | 999 | 999 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[2].u_mult | pipelined_mult_32x32_3 | 1062 | 1062 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[3].u_mult | pipelined_mult_32x32_4 | 997 | 997 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1788 | 1788 | 0 | 0 | 1476 | 0 | 1 | 0 |
|
||||
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 751 | 751 | 0 | 0 | 1180 | 0 | 0 | 0 |
|
||||
| u_core_engine | snix_axi_mm2mm | 1038 | 1038 | 0 | 0 | 296 | 0 | 1 | 0 |
|
||||
| (u_core_engine) | snix_axi_mm2mm | 762 | 762 | 0 | 0 | 243 | 0 | 0 | 0 |
|
||||
| axis_fifo_u0 | snix_axis_fifo | 276 | 276 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
| u_fifo | snix_sync_fifo | 276 | 276 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
| u_sha3 | sha3_top_shared | 1975 | 1975 | 0 | 0 | 2388 | 0 | 0 | 0 |
|
||||
| u_snt | sample_ntt_sync_shared | 2108 | 2108 | 0 | 0 | 1669 | 0 | 0 | 0 |
|
||||
| u_matmul_axi_slave | matmul_axi_slave | 10204 | 10022 | 176 | 6 | 3239 | 0 | 0 | 0 |
|
||||
| (u_matmul_axi_slave) | matmul_axi_slave | 6085 | 5903 | 176 | 6 | 2471 | 0 | 0 | 0 |
|
||||
| mult_inst[0].u_mult | pipelined_mult_32x32 | 1061 | 1061 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[1].u_mult | pipelined_mult_32x32_1 | 998 | 998 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[2].u_mult | pipelined_mult_32x32_2 | 1063 | 1063 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[3].u_mult | pipelined_mult_32x32_3 | 997 | 997 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1558 | 1558 | 0 | 0 | 1476 | 0 | 1 | 0 |
|
||||
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 587 | 587 | 0 | 0 | 1180 | 0 | 0 | 0 |
|
||||
| u_core_engine | snix_axi_mm2mm | 974 | 974 | 0 | 0 | 296 | 0 | 1 | 0 |
|
||||
| (u_core_engine) | snix_axi_mm2mm | 700 | 700 | 0 | 0 | 243 | 0 | 0 | 0 |
|
||||
| axis_fifo_u0 | snix_axis_fifo | 274 | 274 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
| u_fifo | snix_sync_fifo | 274 | 274 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining
|
||||
|
||||
|
||||
@@ -1,28 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:13 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_clock_interaction -file /home/fallensigh/vivado_reports_nodsp/clock_interaction.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock Interaction Report
|
||||
|
||||
Clock Interaction Table
|
||||
-----------------------
|
||||
|
||||
WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock
|
||||
From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints
|
||||
----------------- ----------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- -------------------
|
||||
cpu_clk cpu_clk rise - rise 2.72 0.00 0 17264 30.32 Clean Timed
|
||||
cpu_clk sys_clk 0 162 Ignored Asynchronous Groups
|
||||
mlkem_clk_clk_pll mlkem_clk_clk_pll rise - rise 10.81 0.00 0 74168 40.00 Clean Timed
|
||||
mlkem_clk_clk_pll sys_clk rise - rise 11.25 0.00 0 61 20.00 Clean Timed
|
||||
sys_clk cpu_clk 0 59 Ignored Asynchronous Groups
|
||||
sys_clk mlkem_clk_clk_pll rise - rise 9.16 0.00 0 112 20.00 Clean Timed
|
||||
sys_clk sys_clk rise - rise 0.17 0.00 0 23704 20.00 Clean Timed
|
||||
|
||||
|
||||
@@ -1,76 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:13 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_clocks -file /home/fallensigh/vivado_reports_nodsp/clocks.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200t-fbg676
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
--------------------------------------------------------------------------------------
|
||||
|
||||
Clock Report
|
||||
|
||||
|
||||
Attributes
|
||||
P: Propagated
|
||||
G: Generated
|
||||
A: Auto-derived
|
||||
R: Renamed
|
||||
V: Virtual
|
||||
I: Inverted
|
||||
S: Pin phase-shifted with Latency mode
|
||||
|
||||
Clock Period(ns) Waveform(ns) Attributes Sources
|
||||
clk 20.000 {0.000 10.000} P {clk}
|
||||
clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
|
||||
cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
|
||||
mlkem_clk_clk_pll 40.000 {0.000 20.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
|
||||
sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
|
||||
|
||||
|
||||
====================================================
|
||||
Generated Clocks
|
||||
====================================================
|
||||
|
||||
Generated Clock : clkfbout_clk_pll
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Multiply By : 1
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
|
||||
|
||||
Generated Clock : cpu_clk
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Edges : {1 2 3}
|
||||
Edge Shifts(ns) : {0.000 5.161 10.323}
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
|
||||
|
||||
Generated Clock : mlkem_clk_clk_pll
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Edges : {1 2 3}
|
||||
Edge Shifts(ns) : {0.000 10.000 20.000}
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2}
|
||||
|
||||
Generated Clock : sys_clk
|
||||
Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
||||
Master Clock : clk
|
||||
Multiply By : 1
|
||||
Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
|
||||
|
||||
|
||||
|
||||
====================================================
|
||||
User Uncertainty
|
||||
====================================================
|
||||
|
||||
|
||||
|
||||
====================================================
|
||||
User Jitter
|
||||
====================================================
|
||||
|
||||
Clock Jitter(ns)
|
||||
clk 0.200
|
||||
|
||||
@@ -1,37 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:35:00 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_design_analysis -complexity -file /home/fallensigh/vivado_reports_nodsp/design_analysis_complexity.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
| Design State : Routed
|
||||
-------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Design Analysis
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Complexity Characteristics (Cells)
|
||||
|
||||
1. Complexity Characteristics (Cells)
|
||||
-------------------------------------
|
||||
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
|
||||
| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM |
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
|
||||
| (top) | soc_top | 0.34 | 3.77 | 118528 | 801(1.2%) | 6978(10.2%) | 9384(13.7%) | 7294(10.7%) | 8477(12.4%) | 35413(51.8%) | 1175 | 16 | 39 | 6020 | 0 |
|
||||
| u_axi_axil_adapter | axi_axil_adapter | 0.50 | 5.92 | 1309 | 0(0.0%) | 8(0.7%) | 43(3.8%) | 100(8.9%) | 200(17.7%) | 776(68.9%) | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 |
|
||||
| u_cdma_matmul_bridge | cdma_matmul_bridge | 0.46 | 2.22 | 1002 | 1(0.3%) | 65(17.1%) | 39(10.3%) | 174(45.8%) | 13(3.4%) | 88(23.2%) | 0 | 0 | 0 | 0 | 0 |
|
||||
| u_cpu | core_top | 0.56 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 |
|
||||
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.56 | 3.75 | 74954 | 362(0.9%) | 3923(9.7%) | 6649(16.4%) | 4109(10.2%) | 4490(11.1%) | 20899(51.7%) | 1169 | 16 | 18 | 5286 | 0 |
|
||||
| u_matmul_axi_slave | matmul_axi_slave | 0.63 | 3.76 | 15159 | 18(0.2%) | 1646(15.2%) | 357(3.3%) | 830(7.6%) | 974(9.0%) | 7026(64.7%) | 6 | 0 | 0 | 413 | 0 |
|
||||
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.36 | 3.45 | 3680 | 136(6.5%) | 181(8.6%) | 405(19.3%) | 255(12.2%) | 342(16.3%) | 776(37.0%) | 0 | 0 | 1 | 4 | 0 |
|
||||
+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+
|
||||
* Complexity Ranges
|
||||
** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal, 0.65 - 0.85 -> high, 0.85 - 1.0 -> very high
|
||||
*** -* -> Not computable as cell size is very small
|
||||
|
||||
|
||||
@@ -1,52 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:29 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_design_analysis -timing -file /home/fallensigh/vivado_reports_nodsp/design_analysis_timing.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
| Design State : Routed
|
||||
-----------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Design Analysis
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Setup Path Characteristics 1-1
|
||||
|
||||
1. Setup Path Characteristics 1-1
|
||||
---------------------------------
|
||||
|
||||
+---------------------------+------------------------------------------------------+
|
||||
| Characteristics | Path #1 |
|
||||
+---------------------------+------------------------------------------------------+
|
||||
| Requirement | 20.000 |
|
||||
| Path Delay | 15.605 |
|
||||
| Logic Delay | 5.343(35%) |
|
||||
| Net Delay | 10.263(65%) |
|
||||
| Clock Skew | -3.858 |
|
||||
| Slack | 0.167 |
|
||||
| Clock Relationship | Safely Timed |
|
||||
| Logic Levels | 9 |
|
||||
| Routes | 9 |
|
||||
| Logical Path | FDRE LUT4 LUT6 LUT5 LUT6 RAMD32 LUT6 LUT5 LUT3 OBUFT |
|
||||
| Start Point Clock | sys_clk |
|
||||
| End Point Clock | sys_clk |
|
||||
| DSP Block | None |
|
||||
| BRAM | None |
|
||||
| IO Crossings | 3 |
|
||||
| Config Crossings | 0 |
|
||||
| SLR Crossings | 0 |
|
||||
| PBlocks | 0 |
|
||||
| High Fanout | 130 |
|
||||
| Dont Touch | 0 |
|
||||
| Mark Debug | 0 |
|
||||
| Start Point Pin Primitive | FDRE/C |
|
||||
| End Point Pin Primitive | ext_ram_data[18] |
|
||||
| Start Point Pin | FSM_sequential_ext_wr_state_reg[1]/C |
|
||||
| End Point Pin | ext_ram_data[18] |
|
||||
+---------------------------+------------------------------------------------------+
|
||||
* Bounding box calculated as % of dimensions for the target device (436, 500)
|
||||
|
||||
|
||||
@@ -1,491 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:33:58 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_drc -file /home/fallensigh/vivado_reports_nodsp/drc.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Routed
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: impl_1
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 90
|
||||
+-----------+----------+----------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+-----------+----------+----------------------------+------------+
|
||||
| CHECK-3 | Warning | Report rule limit reached | 2 |
|
||||
| DPIP-1 | Warning | Input pipelining | 16 |
|
||||
| DPOP-1 | Warning | PREG Output pipelining | 16 |
|
||||
| DPOP-2 | Warning | MREG Output pipelining | 16 |
|
||||
| REQP-1839 | Warning | RAMB36 async control check | 20 |
|
||||
| REQP-1840 | Warning | RAMB18 async control check | 20 |
|
||||
+-----------+----------+----------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
CHECK-3#1 Warning
|
||||
Report rule limit reached
|
||||
REQP-1839 rule limit reached: 20 violations have been found.
|
||||
Related violations: <none>
|
||||
|
||||
CHECK-3#2 Warning
|
||||
Report rule limit reached
|
||||
REQP-1840 rule limit reached: 20 violations have been found.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#1 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#2 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#3 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#4 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#5 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#6 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#7 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#8 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#9 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#10 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#11 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#12 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#13 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#14 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#15 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#16 Warning
|
||||
Input pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#1 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#2 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#3 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#4 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#5 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#6 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#7 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#8 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#9 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#10 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#11 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#12 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#13 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#14 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#15 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#16 Warning
|
||||
PREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#1 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#2 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#3 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#4 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#5 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#6 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#7 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#8 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#9 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#10 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#11 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#12 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#13 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#14 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#15 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#16 Warning
|
||||
MREG Output pipelining
|
||||
DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#1 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#2 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#3 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#4 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#5 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#6 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#7 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#8 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#9 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#10 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#11 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#12 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#13 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#14 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#15 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#16 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#17 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#18 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#19 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1839#20 Warning
|
||||
RAMB36 async control check
|
||||
The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#1 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#2 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#3 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#4 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#5 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#6 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#7 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#8 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#9 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#10 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#11 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#12 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#13 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#14 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#15 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#16 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#17 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#18 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#19 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
REQP-1840#20 Warning
|
||||
RAMB18 async control check
|
||||
The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
@@ -1,221 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:13 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/vivado_reports_nodsp/high_fanout.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200t
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
High Fan-out Nets Information
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
| Net Name | Fanout | Driver Type |
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/delay_reg[1] | 24598 | LUT5 |
|
||||
| pll_clk.u_clk_pll/inst/sys_clk | 10004 | BUFG |
|
||||
| pll_clk.u_rst_sys/p_0_in | 4130 | LUT1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0] | 2048 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_n_0 | 1619 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_0[0] | 1608 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 | 1608 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state[2]_i_3_n_0 | 1604 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sel_cbd | 1603 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 | 1601 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 | 1601 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_6_n_0 | 1601 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_7_n_0 | 1601 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 | 1600 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[1] | 1543 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[2] | 1542 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1109 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE |
|
||||
| pll_clk.u_rst_mlkem/delay_reg[1]_0 | 1069 | LUT1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_mb_en0 | 936 | LUT5 |
|
||||
| u_cpu/reset | 799 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[0] | 769 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[1] | 769 | CARRY4 |
|
||||
| u_matmul_axi_slave/w_addr[2] | 724 | FDRE |
|
||||
| u_cpu/u_mul/E[0] | 716 | LUT1 |
|
||||
| u_matmul_axi_slave/w_addr[3] | 628 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r1 | 528 | LUT6 |
|
||||
| u_matmul_axi_slave/current_r_offset[2] | 522 | LUT5 |
|
||||
| u_matmul_axi_slave/current_r_offset[3] | 520 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[0] | 516 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[1] | 516 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[0]_rep_2[0] | 512 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[2] | 390 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[2] | 385 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_vld_reg_n_0 | 370 | FDCE |
|
||||
| u_cpu/wb_stage/w_index[0] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[1] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[2] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[3] | 358 | LUT6 |
|
||||
| u_cpu/wb_stage/w_index[4] | 358 | LUT6 |
|
||||
| u_matmul_axi_slave/acc_idx_d4[0] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[1] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[2] | 354 | FDRE |
|
||||
| u_matmul_axi_slave/acc_idx_d4[3] | 354 | FDRE |
|
||||
| u_cpu/wb_stage/we_0 | 324 | LUT4 |
|
||||
| u_matmul_axi_slave/w_addr[4] | 317 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 290 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[3] | 284 | FDCE |
|
||||
| u_matmul_axi_slave/cur_bank_reg_n_0 | 277 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 263 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 263 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 262 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 261 | RAMB18E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 261 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 261 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[4] | 260 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 259 | RAMB36E1 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 259 | RAMB36E1 |
|
||||
| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0 | 259 | FDRE |
|
||||
| u_matmul_axi_slave/pipe_cnt_reg[1]_rep_n_0 | 257 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[0] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[10] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[11] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[1] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[2] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[5] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[6] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[7] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[8] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[9] | 256 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_active_reg_rep__7[0] | 256 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 |
|
||||
| u_matmul_axi_slave/m_in_b[0][31]_i_1_n_0 | 256 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 |
|
||||
| u_matmul_axi_slave/w_addr[5] | 246 | FDRE |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT3 |
|
||||
| u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 |
|
||||
| u_cpu/mem_stage/E[0] | 234 | LUT6 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8] | 234 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9] | 234 | FDCE |
|
||||
| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 229 | LUT3 |
|
||||
| u_matmul_axi_slave/m_in_b[0][31]_i_7_n_0 | 228 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1] | 227 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[382]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[510]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0 | 224 | LUT4 |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 |
|
||||
| u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 |
|
||||
| u_cpu/u_csr/tlbw_r_tlbidx[2] | 210 | FDRE |
|
||||
| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0] | 203 | FDRE |
|
||||
| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[1] | 203 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[6] | 200 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4] | 200 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[3] | 197 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/grp_ptr_r_reg_n_0_[2] | 196 | FDCE |
|
||||
| u_snix_axil_cdma_mux_8ch/ADDRA[0] | 196 | LUT6 |
|
||||
| u_cpu/wb_stage/Q[33] | 194 | FDRE |
|
||||
| u_cpu/wb_stage/Q[34] | 194 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[5] | 194 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[3] | 193 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r_reg[4]_rep_n_0 | 191 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[2] | 187 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[3] | 187 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1] | 187 | FDCE |
|
||||
| u_matmul_axi_slave/current_r_offset[4] | 187 | LUT5 |
|
||||
| u_matmul_axi_slave/s_axi_wready_reg_1 | 181 | LUT3 |
|
||||
| u_cpu/wb_stage/ws_valid_reg_0 | 180 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[3] | 180 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 177 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[0] | 176 | FDCE |
|
||||
| u_matmul_axi_slave/p_0_in__0 | 176 | LUT4 |
|
||||
| u_matmul_axi_slave/p_0_in__0__0 | 176 | LUT4 |
|
||||
| u_cpu/wb_stage/Q[37] | 173 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[7] | 173 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]_i_4_n_7 | 171 | CARRY4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[127]_i_2_n_0 | 169 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[383]_i_2_n_0 | 169 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[639]_i_2_n_0 | 169 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[895]_i_2_n_0 | 169 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 169 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[5] | 166 | FDCE |
|
||||
| u_cpu/wb_stage/Q[32] | 164 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0] | 164 | FDCE |
|
||||
| u_cpu/wb_stage/Q[35] | 163 | FDRE |
|
||||
| u_cpu/wb_stage/Q[36] | 162 | FDRE |
|
||||
| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0 | 161 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1023]_i_2_n_0 | 160 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[255]_i_2_n_0 | 160 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[511]_i_2_n_0 | 160 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[767]_i_2_n_0 | 160 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3] | 155 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[6] | 153 | FDCE |
|
||||
| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 153 | LUT3 |
|
||||
| u_cpu/axi_bridge/FSM_sequential_write_requst_state_reg[1]_0 | 151 | FDRE |
|
||||
| u_snix_axil_cdma_mux_8ch/u_core_engine/num_bytes_comb1 | 150 | CARRY4 |
|
||||
| u_cpu/dcache/awaddr[31]_i_3_n_0 | 148 | LUT2 |
|
||||
| u_cpu/dcache/awaddr[31]_i_4_n_0 | 148 | LUT2 |
|
||||
| u_matmul_axi_slave/s_axi_wready_reg_0 | 148 | LUT5 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[0] | 145 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_63_n_0 | 144 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6] | 143 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6] | 143 | FDCE |
|
||||
| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0 | 143 | LUT3 |
|
||||
| u_matmul_axi_slave/pipe_cnt[3]_i_4_n_0 | 143 | LUT3 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep_n_0 | 142 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4] | 141 | FDCE |
|
||||
| u_cpu/dcache/write_buffer_state | 140 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_reg_rep__6_n_0 | 140 | FDCE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[5] | 140 | FDCE |
|
||||
| u_cpu/u_csr/tlbw_r_tlbidx[0] | 139 | FDRE |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_37_n_0 | 139 | LUT4 |
|
||||
| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep__3_n_0 | 139 | FDCE |
|
||||
+---------------------------------------------------------------------------------------+--------+-------------+
|
||||
|
||||
|
||||
@@ -1,542 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:05 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_methodology -file /home/fallensigh/vivado_reports_nodsp/methodology.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Routed
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Methodology
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: impl_1
|
||||
Design limits: <entire design considered>
|
||||
Max violations: <unlimited>
|
||||
Violations found: 99
|
||||
+-----------+----------+-------------------------------------------------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+-----------+----------+-------------------------------------------------------------------+------------+
|
||||
| LUTAR-1 | Warning | LUT drives async reset alert | 1 |
|
||||
| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 8 |
|
||||
| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 1 |
|
||||
| SYNTH-16 | Warning | Address collision | 8 |
|
||||
| TIMING-10 | Warning | Missing property on synchronizer | 1 |
|
||||
| TIMING-18 | Warning | Missing input or output delay | 76 |
|
||||
| TIMING-47 | Warning | False path or asynchronous clock group between synchronous clocks | 2 |
|
||||
| XDCC-1 | Warning | Scoped Clock constraint overwritten with the same name | 1 |
|
||||
| XDCC-7 | Warning | Scoped Clock constraint overwritten on the same source | 1 |
|
||||
+-----------+----------+-------------------------------------------------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
LUTAR-1#1 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24584 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-5#1 Warning
|
||||
Mapped onto distributed RAM because of timing constraints
|
||||
The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-5#2 Warning
|
||||
Mapped onto distributed RAM because of timing constraints
|
||||
The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-5#3 Warning
|
||||
Mapped onto distributed RAM because of timing constraints
|
||||
The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-5#4 Warning
|
||||
Mapped onto distributed RAM because of timing constraints
|
||||
The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-5#5 Warning
|
||||
Mapped onto distributed RAM because of timing constraints
|
||||
The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-5#6 Warning
|
||||
Mapped onto distributed RAM because of timing constraints
|
||||
The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-5#7 Warning
|
||||
Mapped onto distributed RAM because of timing constraints
|
||||
The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-5#8 Warning
|
||||
Mapped onto distributed RAM because of timing constraints
|
||||
The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-6#1 Warning
|
||||
Timing of a block RAM might be sub-optimal
|
||||
The timing for the instance u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-16#1 Warning
|
||||
Address collision
|
||||
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-16#2 Warning
|
||||
Address collision
|
||||
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-16#3 Warning
|
||||
Address collision
|
||||
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-16#4 Warning
|
||||
Address collision
|
||||
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-16#5 Warning
|
||||
Address collision
|
||||
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-16#6 Warning
|
||||
Address collision
|
||||
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-16#7 Warning
|
||||
Address collision
|
||||
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-16#8 Warning
|
||||
Address collision
|
||||
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-10#1 Warning
|
||||
Missing property on synchronizer
|
||||
One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#1 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on UART_RX relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#2 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on UART_TX relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#3 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[0] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#4 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[10] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#5 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[11] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#6 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[12] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#7 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[13] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#8 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[14] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#9 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[15] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#10 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[16] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#11 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[17] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#12 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[18] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#13 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[19] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#14 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[1] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#15 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[20] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#16 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[21] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#17 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[22] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#18 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[23] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#19 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[24] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#20 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[25] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#21 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[26] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#22 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[27] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#23 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[28] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#24 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[29] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#25 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[2] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#26 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[30] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#27 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[31] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#28 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[3] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#29 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[4] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#30 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[5] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#31 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[6] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#32 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[7] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#33 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[8] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#34 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on dip_sw[9] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#35 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on touch_btn[0] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#36 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on touch_btn[1] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#37 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on touch_btn[2] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#38 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on touch_btn[3] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#39 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy0[0] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#40 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy0[1] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#41 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy0[2] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#42 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy0[3] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#43 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy0[4] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#44 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy0[5] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#45 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy0[6] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#46 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy0[7] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#47 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy1[0] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#48 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy1[1] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#49 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy1[2] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#50 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy1[3] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#51 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy1[4] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#52 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy1[5] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#53 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy1[6] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#54 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on dpy1[7] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#55 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[0] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#56 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[10] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#57 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[11] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#58 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[12] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#59 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[13] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#60 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[14] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#61 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[15] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#62 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[1] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#63 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[2] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#64 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[3] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#65 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[4] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#66 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[5] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#67 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[6] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#68 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[7] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#69 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[8] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#70 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on leds[9] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#71 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on video_de relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#72 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on video_hsync relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#73 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on video_red[0] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#74 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on video_red[1] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#75 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on video_red[2] relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#76 Warning
|
||||
Missing input or output delay
|
||||
An output delay is missing on video_vsync relative to clock(s) clk
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-47#1 Warning
|
||||
False path or asynchronous clock group between synchronous clocks
|
||||
A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-47#2 Warning
|
||||
False path or asynchronous clock group between synchronous clocks
|
||||
A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
|
||||
Related violations: <none>
|
||||
|
||||
XDCC-1#1 Warning
|
||||
Scoped Clock constraint overwritten with the same name
|
||||
A new clock constraint create_clock overrides a previous scoped clock constraint with the same name. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
|
||||
New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4))
|
||||
Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
|
||||
Related violations: <none>
|
||||
|
||||
XDCC-7#1 Warning
|
||||
Scoped Clock constraint overwritten on the same source
|
||||
A new clock constraint create_clock overrides a previous scoped clock constraint defined on the same source. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
|
||||
New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4))
|
||||
Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,180 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:25 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_power -file /home/fallensigh/vivado_reports_nodsp/power.rpt
|
||||
| Design : soc_top
|
||||
| Device : xc7a200tfbg676-1
|
||||
| Design State : routed
|
||||
| Grade : commercial
|
||||
| Process : typical
|
||||
| Characterization : Production
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Power Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
1.1 On-Chip Components
|
||||
1.2 Power Supply Summary
|
||||
1.3 Confidence Level
|
||||
2. Settings
|
||||
2.1 Environment
|
||||
2.2 Clock Constraints
|
||||
3. Detailed Reports
|
||||
3.1 By Hierarchy
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
| Total On-Chip Power (W) | 0.549 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 0.409 |
|
||||
| Device Static (W) | 0.141 |
|
||||
| Effective TJA (C/W) | 1.9 |
|
||||
| Max Ambient (C) | 84.0 |
|
||||
| Junction Temperature (C) | 26.0 |
|
||||
| Confidence Level | Low |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
| Design Nets Matched | NA |
|
||||
+--------------------------+--------------+
|
||||
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
|
||||
|
||||
|
||||
1.1 On-Chip Components
|
||||
----------------------
|
||||
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| Clocks | 0.042 | 7 | --- | --- |
|
||||
| Slice Logic | 0.069 | 120086 | --- | --- |
|
||||
| LUT as Logic | 0.064 | 63754 | 133800 | 47.65 |
|
||||
| CARRY4 | 0.002 | 2859 | 33450 | 8.55 |
|
||||
| LUT as Distributed RAM | <0.001 | 740 | 46200 | 1.60 |
|
||||
| Register | <0.001 | 39931 | 267600 | 14.92 |
|
||||
| LUT as Shift Register | <0.001 | 1175 | 46200 | 2.54 |
|
||||
| F7/F8 Muxes | <0.001 | 6036 | 133800 | 4.51 |
|
||||
| Others | 0.000 | 318 | --- | --- |
|
||||
| Signals | 0.115 | 85084 | --- | --- |
|
||||
| Block RAM | 0.019 | 23.5 | 365 | 6.44 |
|
||||
| PLL | 0.132 | 1 | 10 | 10.00 |
|
||||
| DSPs | 0.009 | 16 | 740 | 2.16 |
|
||||
| I/O | 0.023 | 202 | 400 | 50.50 |
|
||||
| Static Power | 0.141 | | | |
|
||||
| Total | 0.549 | | | |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
1.2 Power Supply Summary
|
||||
------------------------
|
||||
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
| Vccint | 1.000 | 0.294 | 0.262 | 0.032 |
|
||||
| Vccaux | 1.800 | 0.099 | 0.069 | 0.031 |
|
||||
| Vcco33 | 3.300 | 0.011 | 0.006 | 0.005 |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
|
||||
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccbram | 1.000 | 0.003 | 0.001 | 0.001 |
|
||||
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
|
||||
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
|
||||
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
|
||||
+-----------+-------------+-----------+-------------+------------+
|
||||
|
||||
|
||||
1.3 Confidence Level
|
||||
--------------------
|
||||
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| Design implementation state | High | Design is routed | |
|
||||
| Clock nodes activity | High | User specified more than 95% of clocks | |
|
||||
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
|
||||
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | Low | | |
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
2. Settings
|
||||
-----------
|
||||
|
||||
2.1 Environment
|
||||
---------------
|
||||
|
||||
+-----------------------+--------------------------+
|
||||
| Ambient Temp (C) | 25.0 |
|
||||
| ThetaJA (C/W) | 1.9 |
|
||||
| Airflow (LFM) | 250 |
|
||||
| Heat Sink | medium (Medium Profile) |
|
||||
| ThetaSA (C/W) | 3.4 |
|
||||
| Board Selection | medium (10"x10") |
|
||||
| # of Board Layers | 12to15 (12 to 15 Layers) |
|
||||
| Board Temperature (C) | 25.0 |
|
||||
+-----------------------+--------------------------+
|
||||
|
||||
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
+-------------------+------------------------------------------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+-------------------+------------------------------------------+-----------------+
|
||||
| clk | clk | 20.0 |
|
||||
| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 |
|
||||
| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 |
|
||||
| mlkem_clk_clk_pll | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 40.0 |
|
||||
| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 |
|
||||
+-------------------+------------------------------------------+-----------------+
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
-------------------
|
||||
|
||||
3.1 By Hierarchy
|
||||
----------------
|
||||
|
||||
+----------------------------+-----------+
|
||||
| Name | Power (W) |
|
||||
+----------------------------+-----------+
|
||||
| soc_top | 0.409 |
|
||||
| pll_clk.u_clk_pll | 0.133 |
|
||||
| inst | 0.133 |
|
||||
| u_Axi_CDC | 0.002 |
|
||||
| u_axi_uart_controller | 0.001 |
|
||||
| uart0 | 0.001 |
|
||||
| regs | 0.001 |
|
||||
| u_cdma_matmul_bridge | 0.001 |
|
||||
| u_cpu | 0.018 |
|
||||
| addr_trans | 0.002 |
|
||||
| tlb_entry | 0.002 |
|
||||
| btb | 0.002 |
|
||||
| dcache | 0.004 |
|
||||
| icache | 0.005 |
|
||||
| u_csr | 0.002 |
|
||||
| u_fft_mlkem_axi_slave | 0.148 |
|
||||
| u_fft_controller | 0.032 |
|
||||
| u_FFT | 0.029 |
|
||||
| u_mlkem_axi_cdc | 0.002 |
|
||||
| u_mlkem_axi_slave | 0.115 |
|
||||
| u_mlkem | 0.113 |
|
||||
| u_matmul_axi_slave | 0.065 |
|
||||
| u_snix_axil_cdma_mux_8ch | 0.009 |
|
||||
| u_core_engine | 0.004 |
|
||||
| axis_fifo_u0 | 0.003 |
|
||||
+----------------------------+-----------+
|
||||
|
||||
|
||||
@@ -1,12 +0,0 @@
|
||||
Design Route Status
|
||||
: # nets :
|
||||
------------------------------------------- : ----------- :
|
||||
# of logical nets.......................... : 128919 :
|
||||
# of nets not needing routing.......... : 43824 :
|
||||
# of internally routed nets........ : 43359 :
|
||||
# of nets with no loads............ : 465 :
|
||||
# of routable nets..................... : 85095 :
|
||||
# of fully routed nets............. : 85095 :
|
||||
# of nets with routing errors.......... : 0 :
|
||||
------------------------------------------- : ----------- :
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,237 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:05 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -file /home/fallensigh/vivado_reports_nodsp/utilization.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Routed
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Slice Logic Distribution
|
||||
3. Memory
|
||||
4. DSP
|
||||
5. IO and GT Specific
|
||||
6. Clocking
|
||||
7. Specific Feature
|
||||
8. Primitives
|
||||
9. Black Boxes
|
||||
10. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
| Slice LUTs | 60995 | 0 | 133800 | 45.59 |
|
||||
| LUT as Logic | 59140 | 0 | 133800 | 44.20 |
|
||||
| LUT as Memory | 1855 | 0 | 46200 | 4.02 |
|
||||
| LUT as Distributed RAM | 740 | 0 | | |
|
||||
| LUT as Shift Register | 1115 | 0 | | |
|
||||
| Slice Registers | 39931 | 0 | 267600 | 14.92 |
|
||||
| Register as Flip Flop | 39931 | 0 | 267600 | 14.92 |
|
||||
| Register as Latch | 0 | 0 | 267600 | 0.00 |
|
||||
| F7 Muxes | 4480 | 0 | 66900 | 6.70 |
|
||||
| F8 Muxes | 1556 | 0 | 33450 | 4.65 |
|
||||
+----------------------------+-------+-------+-----------+-------+
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 24 | Yes | - | Set |
|
||||
| 26637 | Yes | - | Reset |
|
||||
| 139 | Yes | Set | - |
|
||||
| 13131 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Slice Logic Distribution
|
||||
---------------------------
|
||||
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
| Slice | 20066 | 0 | 33450 | 59.99 |
|
||||
| SLICEL | 13210 | 0 | | |
|
||||
| SLICEM | 6856 | 0 | | |
|
||||
| LUT as Logic | 59140 | 0 | 133800 | 44.20 |
|
||||
| using O5 output only | 2 | | | |
|
||||
| using O6 output only | 49931 | | | |
|
||||
| using O5 and O6 | 9207 | | | |
|
||||
| LUT as Memory | 1855 | 0 | 46200 | 4.02 |
|
||||
| LUT as Distributed RAM | 740 | 0 | | |
|
||||
| using O5 output only | 0 | | | |
|
||||
| using O6 output only | 60 | | | |
|
||||
| using O5 and O6 | 680 | | | |
|
||||
| LUT as Shift Register | 1115 | 0 | | |
|
||||
| using O5 output only | 47 | | | |
|
||||
| using O6 output only | 1008 | | | |
|
||||
| using O5 and O6 | 60 | | | |
|
||||
| Slice Registers | 39931 | 0 | 267600 | 14.92 |
|
||||
| Register driven from within the Slice | 20433 | | | |
|
||||
| Register driven from outside the Slice | 19498 | | | |
|
||||
| LUT in front of the register is unused | 10788 | | | |
|
||||
| LUT in front of the register is used | 8710 | | | |
|
||||
| Unique Control Sets | 1304 | | 33450 | 3.90 |
|
||||
+--------------------------------------------+-------+-------+-----------+-------+
|
||||
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
|
||||
3. Memory
|
||||
---------
|
||||
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 23.5 | 0 | 365 | 6.44 |
|
||||
| RAMB36/FIFO* | 8 | 0 | 365 | 2.19 |
|
||||
| RAMB36E1 only | 8 | | | |
|
||||
| RAMB18 | 31 | 0 | 730 | 4.25 |
|
||||
| RAMB18E1 only | 31 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
4. DSP
|
||||
------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| DSPs | 16 | 0 | 740 | 2.16 |
|
||||
| DSP48E1 only | 16 | | | |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 202 | 202 | 400 | 50.50 |
|
||||
| IOB Master Pads | 97 | | | |
|
||||
| IOB Slave Pads | 102 | | | |
|
||||
| Bonded IPADs | 0 | 0 | 26 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 16 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 10 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 384 | 0.00 |
|
||||
| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 400 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 400 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 4 | 0 | 32 | 12.50 |
|
||||
| BUFIO | 0 | 0 | 40 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| PLLE2_ADV | 1 | 0 | 10 | 10.00 |
|
||||
| BUFMRCE | 0 | 0 | 20 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 120 | 0.00 |
|
||||
| BUFR | 0 | 0 | 40 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
8. Primitives
|
||||
-------------
|
||||
|
||||
+-----------+-------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+-----------+-------+---------------------+
|
||||
| LUT6 | 35413 | LUT |
|
||||
| FDCE | 26637 | Flop & Latch |
|
||||
| FDRE | 13131 | Flop & Latch |
|
||||
| LUT3 | 9384 | LUT |
|
||||
| LUT5 | 8477 | LUT |
|
||||
| LUT4 | 7294 | LUT |
|
||||
| LUT2 | 6978 | LUT |
|
||||
| MUXF7 | 4480 | MuxFx |
|
||||
| CARRY4 | 2859 | CarryLogic |
|
||||
| MUXF8 | 1556 | MuxFx |
|
||||
| RAMD32 | 1060 | Distributed Memory |
|
||||
| SRLC32E | 992 | Distributed Memory |
|
||||
| LUT1 | 801 | LUT |
|
||||
| RAMS32 | 328 | Distributed Memory |
|
||||
| SRL16E | 183 | Distributed Memory |
|
||||
| FDSE | 139 | Flop & Latch |
|
||||
| IBUF | 104 | IO |
|
||||
| OBUF | 98 | IO |
|
||||
| OBUFT | 66 | IO |
|
||||
| RAMD64E | 32 | Distributed Memory |
|
||||
| RAMB18E1 | 31 | Block Memory |
|
||||
| FDPE | 24 | Flop & Latch |
|
||||
| DSP48E1 | 16 | Block Arithmetic |
|
||||
| RAMB36E1 | 8 | Block Memory |
|
||||
| BUFG | 4 | Clock |
|
||||
| PLLE2_ADV | 1 | Clock |
|
||||
+-----------+-------+---------------------+
|
||||
|
||||
|
||||
9. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
10. Instantiated Netlists
|
||||
-------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
| clk_pll | 1 |
|
||||
+----------+------+
|
||||
|
||||
|
||||
@@ -1,276 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
||||
| Date : Wed Jul 8 03:34:06 2026
|
||||
| Host : fedora running 64-bit unknown
|
||||
| Command : report_utilization -hierarchical -file /home/fallensigh/vivado_reports_nodsp/utilization_hier.rpt
|
||||
| Design : soc_top
|
||||
| Device : 7a200tfbg676-1
|
||||
| Design State : Routed
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Utilization by Hierarchy
|
||||
|
||||
1. Utilization by Hierarchy
|
||||
---------------------------
|
||||
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
| soc_top | (top) | 60995 | 59140 | 740 | 1115 | 39931 | 8 | 31 | 16 |
|
||||
| (soc_top) | (top) | 878 | 822 | 56 | 0 | 4 | 0 | 0 | 0 |
|
||||
| pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| inst | clk_pll__clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_mlkem | rst_sync_0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| pll_clk.u_rst_sys | rst_sync_1 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 459 | 459 | 0 | 0 | 151 | 0 | 0 | 0 |
|
||||
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 6 | 6 | 0 | 0 | 24 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_82 | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_65 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_81 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_66 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_80 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_67 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_79 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_76 | 27 | 27 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_77 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_78 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_73 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_74 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_75 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7_70 | 20 | 20 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_71 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3_72 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 23 | 23 | 0 | 0 | 11 | 0 | 0 | 0 |
|
||||
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| cmdArbiter | StreamArbiter_7 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
|
||||
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| fifo | StreamFifo_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 96 | 96 | 0 | 0 | 25 | 0 | 0 | 0 |
|
||||
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 75 | 75 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4ReadOnlyErrorSlave_1_69 | 21 | 21 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 40 | 40 | 0 | 0 | 18 | 0 | 0 | 0 |
|
||||
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 20 | 20 | 0 | 0 | 16 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1_68 | 21 | 21 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 133 | 133 | 0 | 0 | 17 | 0 | 0 | 0 |
|
||||
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 118 | 118 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
|
||||
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 30 | 30 | 0 | 0 | 14 | 0 | 0 | 0 |
|
||||
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 18 | 18 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| u_Axi_CDC | Axi_CDC | 410 | 282 | 128 | 0 | 317 | 0 | 0 | 0 |
|
||||
| arFifo | StreamFifoCC_3_48 | 181 | 145 | 36 | 0 | 77 | 0 | 0 | 0 |
|
||||
| (arFifo) | StreamFifoCC_3_48 | 176 | 140 | 36 | 0 | 65 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_63 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_64 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| awFifo | StreamFifoCC_49 | 103 | 67 | 36 | 0 | 79 | 0 | 0 | 0 |
|
||||
| (awFifo) | StreamFifoCC_49 | 99 | 63 | 36 | 0 | 65 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_10_60 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_61 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_62 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| bFifo | StreamFifoCC_2_50 | 15 | 15 | 0 | 0 | 26 | 0 | 0 | 0 |
|
||||
| (bFifo) | StreamFifoCC_2_50 | 8 | 8 | 0 | 0 | 12 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_5_57 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_4_58 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_6_59 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| rFifo | StreamFifoCC_4_51 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 |
|
||||
| (rFifo) | StreamFifoCC_4_51 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_55 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_1_56 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| wFifo | StreamFifoCC_1_52 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 |
|
||||
| (wFifo) | StreamFifoCC_1_52 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_7_53 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_8_54 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_axi_axil_adapter | axi_axil_adapter | 1073 | 1073 | 0 | 0 | 173 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 498 | 498 | 0 | 0 | 85 | 0 | 0 | 0 |
|
||||
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 575 | 575 | 0 | 0 | 88 | 0 | 0 | 0 |
|
||||
| u_axi_dvi | axi_dvi | 283 | 283 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| u_axi_ram | axi_wrap_ram_sp_external | 350 | 350 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| u_axi_sram_sp | axi2sram_sp_external | 350 | 350 | 0 | 0 | 78 | 0 | 0 | 0 |
|
||||
| u_axi_uart_controller | axi_uart_controller | 683 | 667 | 16 | 0 | 457 | 0 | 0 | 0 |
|
||||
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 251 | 251 | 0 | 0 | 120 | 0 | 0 | 0 |
|
||||
| uart0 | UART_TOP | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| regs | uart_regs | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 |
|
||||
| (regs) | uart_regs | 119 | 119 | 0 | 0 | 155 | 0 | 0 | 0 |
|
||||
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 |
|
||||
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
|
||||
| fifo_rx | uart_rfifo | 161 | 153 | 8 | 0 | 70 | 0 | 0 | 0 |
|
||||
| (fifo_rx) | uart_rfifo | 143 | 143 | 0 | 0 | 62 | 0 | 0 | 0 |
|
||||
| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 |
|
||||
| (transmitter) | uart_transmitter | 41 | 41 | 0 | 0 | 35 | 0 | 0 | 0 |
|
||||
| fifo_tx | uart_tfifo | 43 | 35 | 8 | 0 | 21 | 0 | 0 | 0 |
|
||||
| (fifo_tx) | uart_tfifo | 24 | 24 | 0 | 0 | 13 | 0 | 0 | 0 |
|
||||
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_cdma_matmul_bridge | cdma_matmul_bridge | 251 | 251 | 0 | 0 | 578 | 0 | 0 | 0 |
|
||||
| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 |
|
||||
| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 |
|
||||
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
|
||||
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
|
||||
| u_cpu | core_top | 8551 | 8299 | 252 | 0 | 5591 | 0 | 20 | 0 |
|
||||
| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 |
|
||||
| addr_trans | addr_trans | 2247 | 2107 | 140 | 0 | 1244 | 0 | 0 | 0 |
|
||||
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
|
||||
| tlb_entry | tlb_entry | 2247 | 2107 | 140 | 0 | 1204 | 0 | 0 | 0 |
|
||||
| axi_bridge | axi_bridge | 40 | 40 | 0 | 0 | 214 | 0 | 0 | 0 |
|
||||
| btb | btb | 1046 | 966 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
||||
| (btb) | btb | 1044 | 964 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
||||
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| dcache | dcache | 552 | 520 | 32 | 0 | 146 | 0 | 10 | 0 |
|
||||
| (dcache) | dcache | 87 | 55 | 32 | 0 | 138 | 0 | 0 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_46 | 41 | 41 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| exe_stage | exe_stage | 663 | 663 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| (exe_stage) | exe_stage | 632 | 632 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| icache | icache | 235 | 235 | 0 | 0 | 55 | 0 | 10 | 0 |
|
||||
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| tagv_ram_way[1].u | tagv_sram_35 | 87 | 87 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| id_stage | id_stage | 1054 | 1054 | 0 | 0 | 108 | 0 | 0 | 0 |
|
||||
| if_stage | if_stage | 135 | 135 | 0 | 0 | 173 | 0 | 0 | 0 |
|
||||
| mem_stage | mem_stage | 116 | 116 | 0 | 0 | 211 | 0 | 0 | 0 |
|
||||
| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 |
|
||||
| u_div | div | 142 | 142 | 0 | 0 | 107 | 0 | 0 | 0 |
|
||||
| u_mul | mul | 936 | 936 | 0 | 0 | 592 | 0 | 0 | 0 |
|
||||
| wb_stage | wb_stage | 680 | 680 | 0 | 0 | 233 | 0 | 0 | 0 |
|
||||
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 36148 | 34927 | 112 | 1109 | 27165 | 8 | 10 | 16 |
|
||||
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| u_fft_controller | fft_controller | 2646 | 1606 | 0 | 1040 | 1083 | 6 | 4 | 16 |
|
||||
| (u_fft_controller) | fft_controller | 123 | 123 | 0 | 0 | 100 | 0 | 0 | 0 |
|
||||
| u_FFT | FFT | 2496 | 1456 | 0 | 1040 | 983 | 6 | 0 | 16 |
|
||||
| SU1 | SdfUnit | 1071 | 303 | 0 | 768 | 197 | 2 | 0 | 4 |
|
||||
| (SU1) | SdfUnit | 205 | 205 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_25 | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer | 562 | 50 | 0 | 512 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized0 | 256 | 0 | 0 | 256 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| TW | Twiddle_27 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU2 | SdfUnit__parameterized0 | 492 | 300 | 0 | 192 | 197 | 2 | 0 | 4 |
|
||||
| (SU2) | SdfUnit__parameterized0 | 73 | 73 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_22 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| TW | Twiddle_23 | 3 | 3 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU3 | SdfUnit__parameterized1 | 346 | 298 | 0 | 48 | 197 | 0 | 0 | 4 |
|
||||
| (SU3) | SdfUnit__parameterized1 | 74 | 74 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_17 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized4 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply_19 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| SU4 | SdfUnit__parameterized2 | 327 | 295 | 0 | 32 | 197 | 2 | 0 | 4 |
|
||||
| (SU4) | SdfUnit__parameterized2 | 69 | 69 | 0 | 0 | 133 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly_15 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0_16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized5 | 128 | 112 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized6 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
||||
| MU | Multiply | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 |
|
||||
| TW | Twiddle | 2 | 2 | 0 | 0 | 0 | 2 | 0 | 0 |
|
||||
| SU5 | SdfUnit__parameterized3 | 260 | 260 | 0 | 0 | 195 | 0 | 0 | 0 |
|
||||
| (SU5) | SdfUnit__parameterized3 | 68 | 68 | 0 | 0 | 99 | 0 | 0 | 0 |
|
||||
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| BF2 | Butterfly__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
||||
| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
|
||||
| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
|
||||
| u_in0 | my_bram0 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_in1 | my_bram0_12 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out0 | my_bram0_13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_out1 | my_bram0_14 | 25 | 25 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_mlkem_axi_cdc | Axi_CDC_5 | 421 | 309 | 112 | 0 | 272 | 0 | 0 | 0 |
|
||||
| arFifo | StreamFifoCC_3 | 53 | 25 | 28 | 0 | 55 | 0 | 0 | 0 |
|
||||
| (arFifo) | StreamFifoCC_3 | 44 | 16 | 28 | 0 | 43 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9_10 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| awFifo | StreamFifoCC | 40 | 16 | 24 | 0 | 49 | 0 | 0 | 0 |
|
||||
| (awFifo) | StreamFifoCC | 31 | 7 | 24 | 0 | 35 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_9 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| bFifo | StreamFifoCC_2 | 18 | 14 | 4 | 0 | 27 | 0 | 0 | 0 |
|
||||
| (bFifo) | StreamFifoCC_2 | 11 | 7 | 4 | 0 | 13 | 0 | 0 | 0 |
|
||||
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_4 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_6 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
|
||||
| rFifo | StreamFifoCC_4 | 57 | 29 | 28 | 0 | 72 | 0 | 0 | 0 |
|
||||
| (rFifo) | StreamFifoCC_4 | 49 | 21 | 28 | 0 | 56 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_1 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| wFifo | StreamFifoCC_1 | 253 | 225 | 28 | 0 | 69 | 0 | 0 | 0 |
|
||||
| (wFifo) | StreamFifoCC_1 | 248 | 220 | 28 | 0 | 53 | 0 | 0 | 0 |
|
||||
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| pushToPopGray_buffercc | BufferCC_8 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
||||
| u_mlkem_axi_slave | mlkem_axi_slave | 33082 | 33013 | 0 | 69 | 25804 | 2 | 6 | 0 |
|
||||
| (u_mlkem_axi_slave) | mlkem_axi_slave | 1202 | 1202 | 0 | 0 | 1068 | 0 | 0 | 0 |
|
||||
| u_mlkem | mlkem_top | 31884 | 31815 | 0 | 69 | 24736 | 2 | 6 | 0 |
|
||||
| (u_mlkem) | mlkem_top | 2738 | 2738 | 0 | 0 | 4960 | 0 | 0 | 0 |
|
||||
| u_bank_a | sd_bram__parameterized0 | 50 | 50 | 0 | 0 | 0 | 1 | 1 | 0 |
|
||||
| u_bank_se | sd_bram__parameterized1 | 70 | 70 | 0 | 0 | 0 | 1 | 0 | 0 |
|
||||
| u_bank_t | sd_bram__parameterized2 | 654 | 654 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_c_in_bram | sd_bram | 1312 | 1312 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_cbd | sample_cbd_sync_shared | 2741 | 2741 | 0 | 0 | 3186 | 0 | 0 | 0 |
|
||||
| u_comp | comp_decomp_sync | 467 | 466 | 0 | 1 | 323 | 0 | 0 | 0 |
|
||||
| u_ct_bram | sd_bram_6 | 13 | 13 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_dkp_bram | sd_bram_7 | 82 | 82 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_ek_bram | sd_bram_8 | 2121 | 2121 | 0 | 0 | 0 | 0 | 1 | 0 |
|
||||
| u_keccak | keccak_core | 5274 | 5274 | 0 | 0 | 1606 | 0 | 0 | 0 |
|
||||
| u_ntt | ntt_core | 8625 | 8582 | 0 | 43 | 3861 | 0 | 0 | 0 |
|
||||
| (u_ntt) | ntt_core | 6101 | 6085 | 0 | 16 | 3358 | 0 | 0 | 0 |
|
||||
| u_bf | butterfly_unit_pipe | 2260 | 2234 | 0 | 26 | 286 | 0 | 0 | 0 |
|
||||
| (u_bf) | butterfly_unit_pipe | 69 | 44 | 0 | 25 | 75 | 0 | 0 | 0 |
|
||||
| u_barrett | barrett_mul_pipe_9 | 2192 | 2191 | 0 | 1 | 211 | 0 | 0 | 0 |
|
||||
| u_scl | barrett_mul_pipe | 265 | 264 | 0 | 1 | 217 | 0 | 0 | 0 |
|
||||
| u_pmul | poly_mul_sync | 3881 | 3856 | 0 | 25 | 6743 | 0 | 0 | 0 |
|
||||
| (u_pmul) | poly_mul_sync | 2434 | 2434 | 0 | 0 | 6280 | 0 | 0 | 0 |
|
||||
| u_bc | basecase_mul_pipe | 1447 | 1422 | 0 | 25 | 463 | 0 | 0 | 0 |
|
||||
| u_sha3 | sha3_top_shared | 1766 | 1766 | 0 | 0 | 2388 | 0 | 0 | 0 |
|
||||
| u_snt | sample_ntt_sync_shared | 2109 | 2109 | 0 | 0 | 1669 | 0 | 0 | 0 |
|
||||
| u_matmul_axi_slave | matmul_axi_slave | 9758 | 9576 | 176 | 6 | 3248 | 0 | 0 | 0 |
|
||||
| (u_matmul_axi_slave) | matmul_axi_slave | 5637 | 5455 | 176 | 6 | 2480 | 0 | 0 | 0 |
|
||||
| mult_inst[0].u_mult | pipelined_mult_32x32 | 1063 | 1063 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[1].u_mult | pipelined_mult_32x32_2 | 999 | 999 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[2].u_mult | pipelined_mult_32x32_3 | 1062 | 1062 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| mult_inst[3].u_mult | pipelined_mult_32x32_4 | 997 | 997 | 0 | 0 | 192 | 0 | 0 | 0 |
|
||||
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1788 | 1788 | 0 | 0 | 1476 | 0 | 1 | 0 |
|
||||
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 751 | 751 | 0 | 0 | 1180 | 0 | 0 | 0 |
|
||||
| u_core_engine | snix_axi_mm2mm | 1038 | 1038 | 0 | 0 | 296 | 0 | 1 | 0 |
|
||||
| (u_core_engine) | snix_axi_mm2mm | 762 | 762 | 0 | 0 | 243 | 0 | 0 | 0 |
|
||||
| axis_fifo_u0 | snix_axis_fifo | 276 | 276 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
| u_fifo | snix_sync_fifo | 276 | 276 | 0 | 0 | 53 | 0 | 1 | 0 |
|
||||
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
||||
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining
|
||||
|
||||
|
||||
@@ -35,12 +35,6 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.PortWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.SENSITIVITY">LEVEL_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_BUSIF"/>
|
||||
@@ -142,7 +136,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">50</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
@@ -265,7 +259,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">31</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
@@ -295,12 +289,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MAX">64.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MIN">2.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__32.97872______0.000______50.0______130.093____123.600</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">_sys_clk__50.00000______0.000______50.0______122.035____123.600</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">mlkem_clk__50.00000______0.000______50.0______122.035____123.600</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
|
||||
@@ -445,7 +439,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">50</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
@@ -544,7 +538,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">31</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
@@ -572,7 +566,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
|
||||
|
||||
@@ -5,14 +5,11 @@
|
||||
// ML-KEM: 0x0000..0x3fff
|
||||
// FFT: 0x8000..0xcfff
|
||||
// Route the low ML-KEM block to ML-KEM and the remaining accelerator window to
|
||||
// FFT.
|
||||
// FFT. ML-KEM runs in the same clock domain as this AXI slave.
|
||||
(* use_dsp = "no" *) module fft_mlkem_axi_slave (
|
||||
input clk,
|
||||
input resetn,
|
||||
|
||||
input mlkem_clk,
|
||||
input mlkem_resetn,
|
||||
|
||||
input [4:0] s_axi_awid,
|
||||
input [31:0] s_axi_awaddr,
|
||||
input [7:0] s_axi_awlen,
|
||||
@@ -116,7 +113,6 @@
|
||||
wire [1:0] mlkem_m_rresp;
|
||||
wire mlkem_m_rlast;
|
||||
wire mlkem_intr_m;
|
||||
(* async_reg = "true" *) reg [1:0] mlkem_intr_sync;
|
||||
|
||||
wire fft_awready, fft_wready, fft_bvalid;
|
||||
wire [4:0] fft_bid;
|
||||
@@ -178,97 +174,48 @@
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk or negedge resetn) begin
|
||||
if (!resetn)
|
||||
mlkem_intr_sync <= 2'b00;
|
||||
else
|
||||
mlkem_intr_sync <= {mlkem_intr_sync[0], mlkem_intr_m};
|
||||
end
|
||||
assign mlkem_intr = mlkem_intr_m;
|
||||
|
||||
assign mlkem_intr = mlkem_intr_sync[1];
|
||||
assign mlkem_awready = mlkem_m_awready;
|
||||
assign mlkem_wready = mlkem_m_wready;
|
||||
assign mlkem_bvalid = mlkem_m_bvalid;
|
||||
assign mlkem_bid = mlkem_m_bid;
|
||||
assign mlkem_bresp = mlkem_m_bresp;
|
||||
assign mlkem_arready = mlkem_m_arready;
|
||||
assign mlkem_rvalid = mlkem_m_rvalid;
|
||||
assign mlkem_rlast = mlkem_m_rlast;
|
||||
assign mlkem_rid = mlkem_m_rid;
|
||||
assign mlkem_rdata = mlkem_m_rdata;
|
||||
assign mlkem_rresp = mlkem_m_rresp;
|
||||
|
||||
Axi_CDC u_mlkem_axi_cdc (
|
||||
.axiInClk (clk),
|
||||
.axiInRstn (resetn),
|
||||
.axiOutClk (mlkem_clk),
|
||||
.axiOutRstn (mlkem_resetn),
|
||||
|
||||
.axiIn_awvalid (s_axi_awvalid && !write_active && (aw_sel == SEL_MLKEM)),
|
||||
.axiIn_awready (mlkem_awready),
|
||||
.axiIn_awaddr (s_axi_awaddr),
|
||||
.axiIn_awid (s_axi_awid),
|
||||
.axiIn_awlen (s_axi_awlen),
|
||||
.axiIn_awsize (s_axi_awsize),
|
||||
.axiIn_awburst (s_axi_awburst),
|
||||
.axiIn_awlock (s_axi_awlock),
|
||||
.axiIn_awcache (s_axi_awcache),
|
||||
.axiIn_awprot (s_axi_awprot),
|
||||
.axiIn_wvalid (s_axi_wvalid && (sel_w == SEL_MLKEM)),
|
||||
.axiIn_wready (mlkem_wready),
|
||||
.axiIn_wdata (s_axi_wdata),
|
||||
.axiIn_wstrb (s_axi_wstrb),
|
||||
.axiIn_wlast (s_axi_wlast),
|
||||
.axiIn_bvalid (mlkem_bvalid),
|
||||
.axiIn_bready (s_axi_bready && (sel_w == SEL_MLKEM)),
|
||||
.axiIn_bid (mlkem_bid),
|
||||
.axiIn_bresp (mlkem_bresp),
|
||||
.axiIn_arvalid (s_axi_arvalid && !read_active && (ar_sel == SEL_MLKEM)),
|
||||
.axiIn_arready (mlkem_arready),
|
||||
.axiIn_araddr (s_axi_araddr),
|
||||
.axiIn_arid (s_axi_arid),
|
||||
.axiIn_arlen (s_axi_arlen),
|
||||
.axiIn_arsize (s_axi_arsize),
|
||||
.axiIn_arburst (s_axi_arburst),
|
||||
.axiIn_arlock (s_axi_arlock),
|
||||
.axiIn_arcache (s_axi_arcache),
|
||||
.axiIn_arprot (s_axi_arprot),
|
||||
.axiIn_rvalid (mlkem_rvalid),
|
||||
.axiIn_rready (s_axi_rready && (sel_r == SEL_MLKEM)),
|
||||
.axiIn_rdata (mlkem_rdata),
|
||||
.axiIn_rid (mlkem_rid),
|
||||
.axiIn_rresp (mlkem_rresp),
|
||||
.axiIn_rlast (mlkem_rlast),
|
||||
|
||||
.axiOut_awvalid (mlkem_m_awvalid),
|
||||
.axiOut_awready (mlkem_m_awready),
|
||||
.axiOut_awaddr (mlkem_m_awaddr),
|
||||
.axiOut_awid (mlkem_m_awid),
|
||||
.axiOut_awlen (mlkem_m_awlen),
|
||||
.axiOut_awsize (mlkem_m_awsize),
|
||||
.axiOut_awburst (mlkem_m_awburst),
|
||||
.axiOut_awlock (mlkem_m_awlock),
|
||||
.axiOut_awcache (mlkem_m_awcache),
|
||||
.axiOut_awprot (mlkem_m_awprot),
|
||||
.axiOut_wvalid (mlkem_m_wvalid),
|
||||
.axiOut_wready (mlkem_m_wready),
|
||||
.axiOut_wdata (mlkem_m_wdata),
|
||||
.axiOut_wstrb (mlkem_m_wstrb),
|
||||
.axiOut_wlast (mlkem_m_wlast),
|
||||
.axiOut_bvalid (mlkem_m_bvalid),
|
||||
.axiOut_bready (mlkem_m_bready),
|
||||
.axiOut_bid (mlkem_m_bid),
|
||||
.axiOut_bresp (mlkem_m_bresp),
|
||||
.axiOut_arvalid (mlkem_m_arvalid),
|
||||
.axiOut_arready (mlkem_m_arready),
|
||||
.axiOut_araddr (mlkem_m_araddr),
|
||||
.axiOut_arid (mlkem_m_arid),
|
||||
.axiOut_arlen (mlkem_m_arlen),
|
||||
.axiOut_arsize (mlkem_m_arsize),
|
||||
.axiOut_arburst (mlkem_m_arburst),
|
||||
.axiOut_arlock (mlkem_m_arlock),
|
||||
.axiOut_arcache (mlkem_m_arcache),
|
||||
.axiOut_arprot (mlkem_m_arprot),
|
||||
.axiOut_rvalid (mlkem_m_rvalid),
|
||||
.axiOut_rready (mlkem_m_rready),
|
||||
.axiOut_rdata (mlkem_m_rdata),
|
||||
.axiOut_rid (mlkem_m_rid),
|
||||
.axiOut_rresp (mlkem_m_rresp),
|
||||
.axiOut_rlast (mlkem_m_rlast)
|
||||
);
|
||||
assign mlkem_m_awvalid = s_axi_awvalid && !write_active && (aw_sel == SEL_MLKEM);
|
||||
assign mlkem_m_awaddr = s_axi_awaddr;
|
||||
assign mlkem_m_awid = s_axi_awid;
|
||||
assign mlkem_m_awlen = s_axi_awlen;
|
||||
assign mlkem_m_awsize = s_axi_awsize;
|
||||
assign mlkem_m_awburst = s_axi_awburst;
|
||||
assign mlkem_m_awlock = s_axi_awlock;
|
||||
assign mlkem_m_awcache = s_axi_awcache;
|
||||
assign mlkem_m_awprot = s_axi_awprot;
|
||||
assign mlkem_m_wvalid = s_axi_wvalid && (sel_w == SEL_MLKEM);
|
||||
assign mlkem_m_wdata = s_axi_wdata;
|
||||
assign mlkem_m_wstrb = s_axi_wstrb;
|
||||
assign mlkem_m_wlast = s_axi_wlast;
|
||||
assign mlkem_m_bready = s_axi_bready && (sel_w == SEL_MLKEM);
|
||||
assign mlkem_m_arvalid = s_axi_arvalid && !read_active && (ar_sel == SEL_MLKEM);
|
||||
assign mlkem_m_araddr = s_axi_araddr;
|
||||
assign mlkem_m_arid = s_axi_arid;
|
||||
assign mlkem_m_arlen = s_axi_arlen;
|
||||
assign mlkem_m_arsize = s_axi_arsize;
|
||||
assign mlkem_m_arburst = s_axi_arburst;
|
||||
assign mlkem_m_arlock = s_axi_arlock;
|
||||
assign mlkem_m_arcache = s_axi_arcache;
|
||||
assign mlkem_m_arprot = s_axi_arprot;
|
||||
assign mlkem_m_rready = s_axi_rready && (sel_r == SEL_MLKEM);
|
||||
|
||||
mlkem_axi_slave u_mlkem_axi_slave (
|
||||
.clk (mlkem_clk),
|
||||
.resetn (mlkem_resetn),
|
||||
.clk (clk),
|
||||
.resetn (resetn),
|
||||
|
||||
.s_axi_awid (mlkem_m_awid),
|
||||
.s_axi_awaddr (mlkem_m_awaddr),
|
||||
|
||||
@@ -1,9 +1,8 @@
|
||||
// mlkem_axi_slave.v — AXI4 (burst) slave wrapper for the ML-KEM core.
|
||||
// Makes the ML-KEM accelerator (KeyGen / Encaps / Decaps) CPU-controllable.
|
||||
//
|
||||
// This slave is placed behind an AXI clock-domain converter. Its AXI side and
|
||||
// mlkem_top both run in mlkem_clk; sys_clk masters reach it through Axi_CDC in
|
||||
// fft_mlkem_axi_slave.
|
||||
// This slave and mlkem_top run in the same clock domain as the shared
|
||||
// FFT/ML-KEM AXI window.
|
||||
//
|
||||
// Register map (byte offsets from base, e.g. virtual 0xbf400000):
|
||||
// 0x000 CTRL W bit0 = start (launches op selected in CONFIG)
|
||||
@@ -27,8 +26,8 @@
|
||||
|
||||
|
||||
module mlkem_axi_slave (
|
||||
input clk, // mlkem_clk AXI-side clock after Axi_CDC
|
||||
input resetn, // mlkem_resetn, active low
|
||||
input clk,
|
||||
input resetn, // active low
|
||||
|
||||
// AXI Write Address Channel
|
||||
input [4:0] s_axi_awid,
|
||||
|
||||
@@ -83,8 +83,6 @@ wire cpu_clk;
|
||||
wire cpu_resetn;
|
||||
wire sys_clk;
|
||||
wire sys_resetn;
|
||||
wire mlkem_clk;
|
||||
wire mlkem_resetn;
|
||||
wire pll_locked;
|
||||
|
||||
generate if(SIMULATION) begin: sim_clk
|
||||
@@ -97,7 +95,6 @@ generate if(SIMULATION) begin: sim_clk
|
||||
|
||||
assign cpu_clk = clk_sim;
|
||||
assign sys_clk = clk;
|
||||
assign mlkem_clk = sys_clk;
|
||||
rst_sync u_rst_sys(
|
||||
.clk(sys_clk),
|
||||
.rst_n_in(~reset),
|
||||
@@ -108,17 +105,11 @@ generate if(SIMULATION) begin: sim_clk
|
||||
.rst_n_in(sys_resetn),
|
||||
.rst_n_out(cpu_resetn)
|
||||
);
|
||||
rst_sync u_rst_mlkem(
|
||||
.clk(mlkem_clk),
|
||||
.rst_n_in(sys_resetn),
|
||||
.rst_n_out(mlkem_resetn)
|
||||
);
|
||||
end
|
||||
else begin: pll_clk
|
||||
clk_pll u_clk_pll(
|
||||
.cpu_clk (cpu_clk),
|
||||
.sys_clk (sys_clk),
|
||||
.mlkem_clk (mlkem_clk),
|
||||
.resetn (~reset),
|
||||
.locked (pll_locked),
|
||||
.clk_in1 (clk)
|
||||
@@ -133,11 +124,6 @@ else begin: pll_clk
|
||||
.rst_n_in(sys_resetn),
|
||||
.rst_n_out(cpu_resetn)
|
||||
);
|
||||
rst_sync u_rst_mlkem(
|
||||
.clk(mlkem_clk),
|
||||
.rst_n_in(sys_resetn),
|
||||
.rst_n_out(mlkem_resetn)
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
@@ -1466,9 +1452,6 @@ fft_mlkem_axi_slave u_fft_mlkem_axi_slave (
|
||||
.clk (sys_clk),
|
||||
.resetn (sys_resetn),
|
||||
|
||||
.mlkem_clk (mlkem_clk),
|
||||
.mlkem_resetn (mlkem_resetn),
|
||||
|
||||
.s_axi_awid (fft_awid ),
|
||||
.s_axi_awaddr (fft_awaddr ),
|
||||
.s_axi_awlen (fft_awlen ),
|
||||
|
||||
97
sdk/software/examples/mlkem_test/result.txt
Normal file
97
sdk/software/examples/mlkem_test/result.txt
Normal file
@@ -0,0 +1,97 @@
|
||||
MLKEM_START
|
||||
MLKEM_INPUTS=STATIC_KAT_COUNT_0
|
||||
MLKEM_LEVELS=k2,k3,k4
|
||||
MLKEM_DIAG_MODE=isolated_sw_cpu_dma
|
||||
MLKEM_DIAG_ITERS=100
|
||||
|
||||
============================================================
|
||||
ML-KEM-512 isolated diagnostic (k=2)
|
||||
EK=800 bytes, DK=1632 bytes, CT=768 bytes
|
||||
EXPECT_EK32=80b70100831d7ee168f47392483119f93863ecb0bc605312d35728876b00f5f5
|
||||
EXPECT_CT32=917e59d1e182a29648a61955a154b304a842f458eba593f3065fb7d744fba24f
|
||||
EXPECT_SS=2b5c52ee72946331983ba050be0f435055c0547901e03559b356517889ea27c5
|
||||
MLKEM512_SW_ONLY_BEGIN iters=100
|
||||
MLKEM512_SW_ONLY_ITERS=100
|
||||
MLKEM512_SW_ONLY_FAILS=0
|
||||
MLKEM512_SW_ONLY_AVG_CYCLES=2588830
|
||||
MLKEM512_SW_ONLY_AVG_US=78449
|
||||
MLKEM512_SW_ONLY_RESULT=PASS
|
||||
MLKEM512_SW_ONLY_END
|
||||
MLKEM512_CPU_ONLY_BEGIN iters=100
|
||||
MLKEM512_CPU_ONLY_ITERS=100
|
||||
MLKEM512_CPU_ONLY_FAILS=0
|
||||
MLKEM512_CPU_ONLY_AVG_CYCLES=196984
|
||||
MLKEM512_CPU_ONLY_AVG_US=5969
|
||||
MLKEM512_CPU_ONLY_RESULT=PASS
|
||||
MLKEM512_CPU_ONLY_END
|
||||
MLKEM512_DMA_ONLY_BEGIN iters=100
|
||||
MLKEM512_DMA_ONLY_ITERS=100
|
||||
MLKEM512_DMA_ONLY_FAILS=0
|
||||
MLKEM512_DMA_ONLY_AVG_CYCLES=93834
|
||||
MLKEM512_DMA_ONLY_AVG_US=2843
|
||||
MLKEM512_DMA_ONLY_RESULT=PASS
|
||||
MLKEM512_DMA_ONLY_END
|
||||
MLKEM512_ISOLATED_FAILS=0
|
||||
MLKEM512_RESULT=PASS
|
||||
|
||||
============================================================
|
||||
ML-KEM-768 isolated diagnostic (k=3)
|
||||
EK=1184 bytes, DK=2400 bytes, CT=1088 bytes
|
||||
EXPECT_EK32=01f60af1dc8e6360ae78b59d4a5042eb9145a269046d6236b8304f305c2d9dcb
|
||||
EXPECT_CT32=16a61ff84787fd4a5f19ca59b3657db3a106a7329e2d62747a2ef85149163109
|
||||
EXPECT_SS=b408d5d115713f0a93047dbbea832e4340787686d59a9a2d106bd662ba0aa035
|
||||
MLKEM768_SW_ONLY_BEGIN iters=100
|
||||
MLKEM768_SW_ONLY_ITERS=100
|
||||
MLKEM768_SW_ONLY_FAILS=0
|
||||
MLKEM768_SW_ONLY_AVG_CYCLES=4057378
|
||||
MLKEM768_SW_ONLY_AVG_US=122950
|
||||
MLKEM768_SW_ONLY_RESULT=PASS
|
||||
MLKEM768_SW_ONLY_END
|
||||
MLKEM768_CPU_ONLY_BEGIN iters=100
|
||||
MLKEM768_CPU_ONLY_ITERS=100
|
||||
MLKEM768_CPU_ONLY_FAILS=0
|
||||
MLKEM768_CPU_ONLY_AVG_CYCLES=291864
|
||||
MLKEM768_CPU_ONLY_AVG_US=8844
|
||||
MLKEM768_CPU_ONLY_RESULT=PASS
|
||||
MLKEM768_CPU_ONLY_END
|
||||
MLKEM768_DMA_ONLY_BEGIN iters=100
|
||||
MLKEM768_DMA_ONLY_ITERS=100
|
||||
MLKEM768_DMA_ONLY_FAILS=0
|
||||
MLKEM768_DMA_ONLY_AVG_CYCLES=140999
|
||||
MLKEM768_DMA_ONLY_AVG_US=4272
|
||||
MLKEM768_DMA_ONLY_RESULT=PASS
|
||||
MLKEM768_DMA_ONLY_END
|
||||
MLKEM768_ISOLATED_FAILS=0
|
||||
MLKEM768_RESULT=PASS
|
||||
|
||||
============================================================
|
||||
ML-KEM-1024 isolated diagnostic (k=4)
|
||||
EK=1568 bytes, DK=3168 bytes, CT=1568 bytes
|
||||
EXPECT_EK32=a8122f376b3f5d355263eba522c43995044beca78b9ba9924b87035490ae78a9
|
||||
EXPECT_CT32=707d18cabcf89670c80003b47d2b8678ad0da4aaad781a3351e82ac3e447e701
|
||||
EXPECT_SS=23f211b84a6ee20c8c29f6e5314c91b414e940513d380add17bd724ab3a13a52
|
||||
MLKEM1024_SW_ONLY_BEGIN iters=100
|
||||
MLKEM1024_SW_ONLY_ITERS=100
|
||||
MLKEM1024_SW_ONLY_FAILS=0
|
||||
MLKEM1024_SW_ONLY_AVG_CYCLES=6030230
|
||||
MLKEM1024_SW_ONLY_AVG_US=182734
|
||||
MLKEM1024_SW_ONLY_RESULT=PASS
|
||||
MLKEM1024_SW_ONLY_END
|
||||
MLKEM1024_CPU_ONLY_BEGIN iters=100
|
||||
MLKEM1024_CPU_ONLY_ITERS=100
|
||||
MLKEM1024_CPU_ONLY_FAILS=0
|
||||
MLKEM1024_CPU_ONLY_AVG_CYCLES=399825
|
||||
MLKEM1024_CPU_ONLY_AVG_US=12115
|
||||
MLKEM1024_CPU_ONLY_RESULT=PASS
|
||||
MLKEM1024_CPU_ONLY_END
|
||||
MLKEM1024_DMA_ONLY_BEGIN iters=100
|
||||
MLKEM1024_DMA_ONLY_ITERS=100
|
||||
MLKEM1024_DMA_ONLY_FAILS=0
|
||||
MLKEM1024_DMA_ONLY_AVG_CYCLES=195912
|
||||
MLKEM1024_DMA_ONLY_AVG_US=5936
|
||||
MLKEM1024_DMA_ONLY_RESULT=PASS
|
||||
MLKEM1024_DMA_ONLY_END
|
||||
MLKEM1024_ISOLATED_FAILS=0
|
||||
MLKEM1024_RESULT=PASS
|
||||
MLKEM_RESULT=PASS
|
||||
MLKEM_DONE
|
||||
Reference in New Issue
Block a user