8693 lines
774 KiB
Plaintext
8693 lines
774 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Fri Jul 10 04:14:54 2026
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| Host : fedora running 64-bit unknown
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| Command : report_timing -from [get_clocks sys_clk] -to [get_clocks sys_clk] -delay_type max -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/mlkem_clk_timing.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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Timing Report
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Slack (MET) : 0.146ns (required time - arrival time)
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Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: base_ram_be_n[3]
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(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Max at Slow Process Corner
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Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
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Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
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Output Delay: 0.300ns
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Clock Path Skew: -3.955ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
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Source Clock Delay (SCD): -2.321ns
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Clock Pessimism Removal (CPR): -0.601ns
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Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.122ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.955 -2.321
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SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
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SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
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net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
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SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
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SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
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net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
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SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
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SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
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net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
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SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
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SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
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net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
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SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
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SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
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0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
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net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
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SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
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SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
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0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
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net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
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SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
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SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
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0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
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net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
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SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
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SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
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0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
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net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
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SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
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SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
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net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
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SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
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SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
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0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
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net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
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SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
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SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
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0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
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net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
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SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
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SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
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net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
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SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
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SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
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net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
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SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
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SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
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net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
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K25 r base_ram_be_n_OBUF[3]_inst/I
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K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
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net (fo=0) 0.000 13.208 base_ram_be_n[3]
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K25 r base_ram_be_n[3] (OUT)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 20.000 20.000 r
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clock source latency -5.674 14.326
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propagated clock network latency
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0.000 14.326
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clock pessimism -0.601 13.725
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clock uncertainty -0.071 13.654
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output delay -0.300 13.354
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-------------------------------------------------------------------
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required time 13.354
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arrival time -13.208
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-------------------------------------------------------------------
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slack 0.146
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Slack (MET) : 0.146ns (required time - arrival time)
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Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: base_ram_be_n[3]
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(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Max at Slow Process Corner
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Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
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Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
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Output Delay: 0.300ns
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Clock Path Skew: -3.955ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
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Source Clock Delay (SCD): -2.321ns
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Clock Pessimism Removal (CPR): -0.601ns
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Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.122ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.955 -2.321
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SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
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SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
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net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
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SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
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SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
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net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
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SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
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SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
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net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
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SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
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SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
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net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
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SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
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SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
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0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
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net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
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SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
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SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
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0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
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net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
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SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
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SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
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0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
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net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
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SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
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SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
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0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
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net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
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SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
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SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
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net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
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SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
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SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
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0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
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net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
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SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
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SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
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0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
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net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
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SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
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SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
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net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
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SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
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SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
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net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
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SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
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SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
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net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
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K25 r base_ram_be_n_OBUF[3]_inst/I
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K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
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net (fo=0) 0.000 13.208 base_ram_be_n[3]
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K25 r base_ram_be_n[3] (OUT)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 20.000 20.000 r
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clock source latency -5.674 14.326
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propagated clock network latency
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0.000 14.326
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clock pessimism -0.601 13.725
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clock uncertainty -0.071 13.654
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output delay -0.300 13.354
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-------------------------------------------------------------------
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required time 13.354
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arrival time -13.208
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-------------------------------------------------------------------
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slack 0.146
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Slack (MET) : 0.146ns (required time - arrival time)
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Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: base_ram_be_n[3]
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(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Max at Slow Process Corner
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Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
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Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
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Output Delay: 0.300ns
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Clock Path Skew: -3.955ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
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Source Clock Delay (SCD): -2.321ns
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Clock Pessimism Removal (CPR): -0.601ns
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Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.122ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.955 -2.321
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SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
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SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
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net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
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SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
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SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.146ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.146ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.146ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.146ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.146ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.146ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.146ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.243ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O
|
|
net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O
|
|
net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51
|
|
SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.951
|
|
-------------------------------------------------------------------
|
|
slack 0.243
|
|
|
|
Slack (MET) : 0.243ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O
|
|
net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O
|
|
net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51
|
|
SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.951
|
|
-------------------------------------------------------------------
|
|
slack 0.243
|
|
|
|
Slack (MET) : 0.243ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O
|
|
net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O
|
|
net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51
|
|
SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.951
|
|
-------------------------------------------------------------------
|
|
slack 0.243
|
|
|
|
Slack (MET) : 0.243ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O
|
|
net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O
|
|
net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51
|
|
SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.951
|
|
-------------------------------------------------------------------
|
|
slack 0.243
|
|
|
|
Slack (MET) : 0.272ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O
|
|
net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O
|
|
net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52
|
|
SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.922
|
|
-------------------------------------------------------------------
|
|
slack 0.272
|
|
|
|
Slack (MET) : 0.272ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O
|
|
net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O
|
|
net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52
|
|
SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.922
|
|
-------------------------------------------------------------------
|
|
slack 0.272
|
|
|
|
Slack (MET) : 0.272ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O
|
|
net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O
|
|
net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52
|
|
SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.922
|
|
-------------------------------------------------------------------
|
|
slack 0.272
|
|
|
|
Slack (MET) : 0.272ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O
|
|
net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O
|
|
net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52
|
|
SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.922
|
|
-------------------------------------------------------------------
|
|
slack 0.272
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.329ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.314ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2
|
|
SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O
|
|
net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0
|
|
SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0
|
|
SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O
|
|
net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307
|
|
SLICE_X76Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.381 17.706
|
|
clock pessimism -0.507 17.199
|
|
clock uncertainty -0.071 17.129
|
|
SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]
|
|
-------------------------------------------------------------------
|
|
required time 17.242
|
|
arrival time -16.913
|
|
-------------------------------------------------------------------
|
|
slack 0.329
|
|
|
|
Slack (MET) : 0.329ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.314ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2
|
|
SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O
|
|
net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0
|
|
SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0
|
|
SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O
|
|
net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307
|
|
SLICE_X76Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.381 17.706
|
|
clock pessimism -0.507 17.199
|
|
clock uncertainty -0.071 17.129
|
|
SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]
|
|
-------------------------------------------------------------------
|
|
required time 17.242
|
|
arrival time -16.913
|
|
-------------------------------------------------------------------
|
|
slack 0.329
|
|
|
|
Slack (MET) : 0.329ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.314ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2
|
|
SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O
|
|
net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0
|
|
SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0
|
|
SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O
|
|
net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307
|
|
SLICE_X76Y142 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.381 17.706
|
|
clock pessimism -0.507 17.199
|
|
clock uncertainty -0.071 17.129
|
|
SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]
|
|
-------------------------------------------------------------------
|
|
required time 17.242
|
|
arrival time -16.913
|
|
-------------------------------------------------------------------
|
|
slack 0.329
|
|
|
|
Slack (MET) : 0.329ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.314ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2
|
|
SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O
|
|
net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0
|
|
SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0
|
|
SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O
|
|
net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307
|
|
SLICE_X76Y142 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.381 17.706
|
|
clock pessimism -0.507 17.199
|
|
clock uncertainty -0.071 17.129
|
|
SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]
|
|
-------------------------------------------------------------------
|
|
required time 17.242
|
|
arrival time -16.913
|
|
-------------------------------------------------------------------
|
|
slack 0.329
|
|
|
|
Slack (MET) : 0.332ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.321ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2
|
|
SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O
|
|
net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0
|
|
SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0
|
|
SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O
|
|
net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177
|
|
SLICE_X79Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.373 17.699
|
|
clock pessimism -0.507 17.192
|
|
clock uncertainty -0.071 17.122
|
|
SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]
|
|
-------------------------------------------------------------------
|
|
required time 17.186
|
|
arrival time -16.854
|
|
-------------------------------------------------------------------
|
|
slack 0.332
|
|
|
|
Slack (MET) : 0.332ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.321ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2
|
|
SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O
|
|
net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0
|
|
SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0
|
|
SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O
|
|
net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177
|
|
SLICE_X79Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.373 17.699
|
|
clock pessimism -0.507 17.192
|
|
clock uncertainty -0.071 17.122
|
|
SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]
|
|
-------------------------------------------------------------------
|
|
required time 17.186
|
|
arrival time -16.854
|
|
-------------------------------------------------------------------
|
|
slack 0.332
|
|
|
|
Slack (MET) : 0.332ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.321ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2
|
|
SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O
|
|
net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0
|
|
SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0
|
|
SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O
|
|
net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177
|
|
SLICE_X79Y145 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.373 17.699
|
|
clock pessimism -0.507 17.192
|
|
clock uncertainty -0.071 17.122
|
|
SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]
|
|
-------------------------------------------------------------------
|
|
required time 17.186
|
|
arrival time -16.854
|
|
-------------------------------------------------------------------
|
|
slack 0.332
|
|
|
|
Slack (MET) : 0.332ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.321ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2
|
|
SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O
|
|
net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0
|
|
SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0
|
|
SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O
|
|
net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177
|
|
SLICE_X79Y145 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.373 17.699
|
|
clock pessimism -0.507 17.192
|
|
clock uncertainty -0.071 17.122
|
|
SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]
|
|
-------------------------------------------------------------------
|
|
required time 17.186
|
|
arrival time -16.854
|
|
-------------------------------------------------------------------
|
|
slack 0.332
|
|
|
|
Slack (MET) : 0.344ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[0]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T
|
|
L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T
|
|
L24 OBUFT (TriStatE_obuft_T_O)
|
|
3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.010 base_ram_data[0]
|
|
L24 r base_ram_data[0] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.010
|
|
-------------------------------------------------------------------
|
|
slack 0.344
|
|
|
|
Slack (MET) : 0.344ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[0]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T
|
|
L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T
|
|
L24 OBUFT (TriStatE_obuft_T_O)
|
|
3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.010 base_ram_data[0]
|
|
L24 r base_ram_data[0] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.010
|
|
-------------------------------------------------------------------
|
|
slack 0.344
|
|
|
|
Slack (MET) : 0.344ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[0]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T
|
|
L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T
|
|
L24 OBUFT (TriStatE_obuft_T_O)
|
|
3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.010 base_ram_data[0]
|
|
L24 r base_ram_data[0] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.010
|
|
-------------------------------------------------------------------
|
|
slack 0.344
|
|
|
|
Slack (MET) : 0.344ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[0]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
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SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
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SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
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net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
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SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
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SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
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0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
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net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
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SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
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SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
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0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
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net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
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SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
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SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
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net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
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SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
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SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
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net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
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SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
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SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
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net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T
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L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T
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L24 OBUFT (TriStatE_obuft_T_O)
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3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O
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net (fo=1, unset) 0.000 13.010 base_ram_data[0]
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L24 r base_ram_data[0] (INOUT)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 20.000 20.000 r
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clock source latency -5.674 14.326
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propagated clock network latency
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0.000 14.326
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clock pessimism -0.601 13.725
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clock uncertainty -0.071 13.654
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output delay -0.300 13.354
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-------------------------------------------------------------------
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required time 13.354
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arrival time -13.010
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-------------------------------------------------------------------
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slack 0.344
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