12241 lines
895 KiB
Plaintext
12241 lines
895 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Fri Jul 10 04:14:54 2026
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| Host : fedora running 64-bit unknown
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| Command : report_timing -delay_type min -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/timing_hold_paths.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Timing Report
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Slack (MET) : 0.040ns (arrival time - required time)
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Source: u_matmul_axi_slave/m_in_b_reg[1][23]/C
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 0.443ns (logic 0.141ns (31.835%) route 0.302ns (68.165%))
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Logic Levels: 0
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Clock Path Skew: 0.333ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.381ns
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Source Clock Delay (SCD): -0.674ns
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Clock Pessimism Removal (CPR): -0.040ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.174 -0.674
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SLICE_X47Y102 FDRE 0.000 -0.674 r u_matmul_axi_slave/m_in_b_reg[1][23]/C
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SLICE_X47Y102 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_matmul_axi_slave/m_in_b_reg[1][23]/Q
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net (fo=1, routed) 0.302 -0.231 u_matmul_axi_slave/mult_inst[1].u_mult/Q[23]
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SLICE_X59Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.566 -0.381
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clock pessimism 0.040 -0.341
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SLICE_X59Y98 FDRE (Hold_fdre_C_D) 0.070 -0.271 u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]
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-------------------------------------------------------------------
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required time 0.271
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arrival time -0.231
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-------------------------------------------------------------------
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slack 0.040
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Slack (MET) : 0.040ns (arrival time - required time)
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Source: u_matmul_axi_slave/m_in_b_reg[1][23]/C
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 0.443ns (logic 0.141ns (31.835%) route 0.302ns (68.165%))
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Logic Levels: 0
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Clock Path Skew: 0.333ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.381ns
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Source Clock Delay (SCD): -0.674ns
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Clock Pessimism Removal (CPR): -0.040ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.174 -0.674
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SLICE_X47Y102 FDRE 0.000 -0.674 r u_matmul_axi_slave/m_in_b_reg[1][23]/C
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SLICE_X47Y102 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_matmul_axi_slave/m_in_b_reg[1][23]/Q
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net (fo=1, routed) 0.302 -0.231 u_matmul_axi_slave/mult_inst[1].u_mult/Q[23]
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SLICE_X59Y98 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.566 -0.381
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clock pessimism 0.040 -0.341
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SLICE_X59Y98 FDRE (Hold_fdre_C_D) 0.070 -0.271 u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]
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-------------------------------------------------------------------
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required time 0.271
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arrival time -0.231
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-------------------------------------------------------------------
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slack 0.040
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Slack (MET) : 0.042ns (arrival time - required time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 0.412ns (logic 0.187ns (45.442%) route 0.225ns (54.558%))
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Logic Levels: 1 (LUT3=1)
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Clock Path Skew: 0.263ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.413ns
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Source Clock Delay (SCD): -0.639ns
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Clock Pessimism Removal (CPR): -0.037ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.209 -0.639
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SLICE_X82Y77 FDCE 0.000 -0.639 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C
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SLICE_X82Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.498 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/Q
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net (fo=3, routed) 0.225 -0.274 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg_n_0_[11]
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SLICE_X85Y77 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/I2
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SLICE_X85Y77 LUT3 (Prop_lut3_I2_O) 0.046 -0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/O
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net (fo=1, routed) 0.000 -0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1_n_0
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SLICE_X85Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.534 -0.413
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clock pessimism 0.037 -0.376
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SLICE_X85Y77 FDCE (Hold_fdce_C_D) 0.107 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]
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-------------------------------------------------------------------
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required time 0.269
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arrival time -0.228
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-------------------------------------------------------------------
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slack 0.042
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Slack (MET) : 0.042ns (arrival time - required time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 0.412ns (logic 0.187ns (45.442%) route 0.225ns (54.558%))
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Logic Levels: 1 (LUT3=1)
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Clock Path Skew: 0.263ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.413ns
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Source Clock Delay (SCD): -0.639ns
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Clock Pessimism Removal (CPR): -0.037ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.209 -0.639
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SLICE_X82Y77 FDCE 0.000 -0.639 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C
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SLICE_X82Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.498 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/Q
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net (fo=3, routed) 0.225 -0.274 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg_n_0_[11]
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SLICE_X85Y77 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/I2
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SLICE_X85Y77 LUT3 (Prop_lut3_I2_O) 0.046 -0.228 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/O
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net (fo=1, routed) 0.000 -0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1_n_0
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SLICE_X85Y77 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.534 -0.413
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clock pessimism 0.037 -0.376
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SLICE_X85Y77 FDCE (Hold_fdce_C_D) 0.107 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]
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-------------------------------------------------------------------
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required time 0.269
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arrival time -0.228
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-------------------------------------------------------------------
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slack 0.042
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Slack (MET) : 0.049ns (arrival time - required time)
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Source: u_cpu/u_csr/csr_tlbelo0_reg[14]/C
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(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I
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(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Path Group: cpu_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
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Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%))
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Logic Levels: 0
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Clock Path Skew: 0.013ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.383ns
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Source Clock Delay (SCD): -0.612ns
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Clock Pessimism Removal (CPR): 0.216ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock cpu_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.236 -0.612
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SLICE_X97Y50 FDRE 0.000 -0.612 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C
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SLICE_X97Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.471 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q
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net (fo=4, routed) 0.068 -0.403 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0
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SLICE_X96Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I
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------------------------------------------------------------------- -------------------
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(clock cpu_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.564 -0.383
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clock pessimism -0.216 -0.599
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SLICE_X96Y50 RAMD32 (Hold_ramd32_CLK_I)
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0.147 -0.452 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA
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-------------------------------------------------------------------
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required time 0.452
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arrival time -0.403
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-------------------------------------------------------------------
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slack 0.049
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Slack (MET) : 0.049ns (arrival time - required time)
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Source: u_cpu/u_csr/csr_tlbelo0_reg[14]/C
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(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I
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(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Path Group: cpu_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
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Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%))
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Logic Levels: 0
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Clock Path Skew: 0.013ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.383ns
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Source Clock Delay (SCD): -0.612ns
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Clock Pessimism Removal (CPR): 0.216ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock cpu_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.236 -0.612
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SLICE_X97Y50 FDRE 0.000 -0.612 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C
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SLICE_X97Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.471 f u_cpu/u_csr/csr_tlbelo0_reg[14]/Q
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net (fo=4, routed) 0.068 -0.403 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0
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SLICE_X96Y50 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I
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------------------------------------------------------------------- -------------------
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(clock cpu_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.564 -0.383
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clock pessimism -0.216 -0.599
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SLICE_X96Y50 RAMD32 (Hold_ramd32_CLK_I)
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0.147 -0.452 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA
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-------------------------------------------------------------------
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required time 0.452
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arrival time -0.403
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-------------------------------------------------------------------
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slack 0.049
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Slack (MET) : 0.049ns (arrival time - required time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 0.382ns (logic 0.141ns (36.898%) route 0.241ns (63.102%))
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Logic Levels: 0
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Clock Path Skew: 0.263ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.487ns
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Source Clock Delay (SCD): -0.710ns
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Clock Pessimism Removal (CPR): -0.040ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.139 -0.710
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SLICE_X85Y170 FDCE 0.000 -0.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C
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SLICE_X85Y170 FDCE (Prop_fdce_C_Q) 0.141 -0.569 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/Q
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net (fo=14, routed) 0.241 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[9]
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SLICE_X81Y171 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.460 -0.487
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clock pessimism 0.040 -0.447
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SLICE_X81Y171 FDCE (Hold_fdce_C_D) 0.070 -0.377 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]
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-------------------------------------------------------------------
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required time 0.377
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arrival time -0.328
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-------------------------------------------------------------------
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slack 0.049
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Slack (MET) : 0.049ns (arrival time - required time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 0.382ns (logic 0.141ns (36.898%) route 0.241ns (63.102%))
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Logic Levels: 0
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Clock Path Skew: 0.263ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.487ns
|
|
Source Clock Delay (SCD): -0.710ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.139 -0.710
|
|
SLICE_X85Y170 FDCE 0.000 -0.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C
|
|
SLICE_X85Y170 FDCE (Prop_fdce_C_Q) 0.141 -0.569 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/Q
|
|
net (fo=14, routed) 0.241 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[9]
|
|
SLICE_X81Y171 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.460 -0.487
|
|
clock pessimism 0.040 -0.447
|
|
SLICE_X81Y171 FDCE (Hold_fdce_C_D) 0.070 -0.377 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 0.377
|
|
arrival time -0.328
|
|
-------------------------------------------------------------------
|
|
slack 0.049
|
|
|
|
Slack (MET) : 0.051ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.211ns (logic 0.141ns (66.741%) route 0.070ns (33.259%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.386ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
SLICE_X67Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C
|
|
SLICE_X67Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q
|
|
net (fo=4, routed) 0.070 -0.404 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0
|
|
SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.561 -0.386
|
|
clock pessimism -0.216 -0.602
|
|
SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.455 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.455
|
|
arrival time -0.404
|
|
-------------------------------------------------------------------
|
|
slack 0.051
|
|
|
|
Slack (MET) : 0.051ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.211ns (logic 0.141ns (66.741%) route 0.070ns (33.259%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.386ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
SLICE_X67Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C
|
|
SLICE_X67Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_cpu/u_csr/csr_tlbelo1_reg[20]/Q
|
|
net (fo=4, routed) 0.070 -0.404 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0
|
|
SLICE_X66Y50 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.561 -0.386
|
|
clock pessimism -0.216 -0.602
|
|
SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.455 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.455
|
|
arrival time -0.404
|
|
-------------------------------------------------------------------
|
|
slack 0.051
|
|
|
|
Slack (MET) : 0.056ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.508ns (logic 0.213ns (41.922%) route 0.295ns (58.078%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.345ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.294ns
|
|
Source Clock Delay (SCD): -0.602ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.246 -0.602
|
|
SLICE_X112Y55 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C
|
|
SLICE_X112Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.438 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/Q
|
|
net (fo=5, routed) 0.295 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[8]
|
|
SLICE_X114Y49 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/I2
|
|
SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.049 -0.094 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/O
|
|
net (fo=1, routed) 0.000 -0.094 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[8]
|
|
SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.653 -0.294
|
|
clock pessimism 0.037 -0.257
|
|
SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.150
|
|
arrival time -0.094
|
|
-------------------------------------------------------------------
|
|
slack 0.056
|
|
|
|
Slack (MET) : 0.056ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.508ns (logic 0.213ns (41.922%) route 0.295ns (58.078%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.345ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.294ns
|
|
Source Clock Delay (SCD): -0.602ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.246 -0.602
|
|
SLICE_X112Y55 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C
|
|
SLICE_X112Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.438 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/Q
|
|
net (fo=5, routed) 0.295 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[8]
|
|
SLICE_X114Y49 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/I2
|
|
SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.049 -0.094 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/O
|
|
net (fo=1, routed) 0.000 -0.094 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[8]
|
|
SLICE_X114Y49 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.653 -0.294
|
|
clock pessimism 0.037 -0.257
|
|
SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.150
|
|
arrival time -0.094
|
|
-------------------------------------------------------------------
|
|
slack 0.056
|
|
|
|
Slack (MET) : 0.061ns (arrival time - required time)
|
|
Source: u_confreg/confreg_int_set_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_confreg/u_int_ctrl/edge_int_state_reg[11]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.376ns (logic 0.246ns (65.365%) route 0.130ns (34.635%))
|
|
Logic Levels: 1 (LUT4=1)
|
|
Clock Path Skew: 0.195ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.335ns
|
|
Source Clock Delay (SCD): -0.494ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.355 -0.494
|
|
SLICE_X8Y49 FDRE 0.000 -0.494 r u_confreg/confreg_int_set_reg[11]/C
|
|
SLICE_X8Y49 FDRE (Prop_fdre_C_Q) 0.148 -0.346 r u_confreg/confreg_int_set_reg[11]/Q
|
|
net (fo=2, routed) 0.130 -0.215 u_confreg/u_int_ctrl/edge_int_state_reg[31]_0[11]
|
|
SLICE_X8Y51 r u_confreg/u_int_ctrl/edge_int_state[11]_i_1/I2
|
|
SLICE_X8Y51 LUT4 (Prop_lut4_I2_O) 0.098 -0.117 r u_confreg/u_int_ctrl/edge_int_state[11]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.117 u_confreg/u_int_ctrl/edge_int_state[11]_i_1_n_0
|
|
SLICE_X8Y51 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.612 -0.335
|
|
clock pessimism 0.037 -0.298
|
|
SLICE_X8Y51 FDCE (Hold_fdce_C_D) 0.120 -0.178 u_confreg/u_int_ctrl/edge_int_state_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 0.178
|
|
arrival time -0.117
|
|
-------------------------------------------------------------------
|
|
slack 0.061
|
|
|
|
Slack (MET) : 0.061ns (arrival time - required time)
|
|
Source: u_confreg/confreg_int_set_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_confreg/u_int_ctrl/edge_int_state_reg[11]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.376ns (logic 0.246ns (65.365%) route 0.130ns (34.635%))
|
|
Logic Levels: 1 (LUT4=1)
|
|
Clock Path Skew: 0.195ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.335ns
|
|
Source Clock Delay (SCD): -0.494ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.355 -0.494
|
|
SLICE_X8Y49 FDRE 0.000 -0.494 r u_confreg/confreg_int_set_reg[11]/C
|
|
SLICE_X8Y49 FDRE (Prop_fdre_C_Q) 0.148 -0.346 f u_confreg/confreg_int_set_reg[11]/Q
|
|
net (fo=2, routed) 0.130 -0.215 u_confreg/u_int_ctrl/edge_int_state_reg[31]_0[11]
|
|
SLICE_X8Y51 f u_confreg/u_int_ctrl/edge_int_state[11]_i_1/I2
|
|
SLICE_X8Y51 LUT4 (Prop_lut4_I2_O) 0.098 -0.117 f u_confreg/u_int_ctrl/edge_int_state[11]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.117 u_confreg/u_int_ctrl/edge_int_state[11]_i_1_n_0
|
|
SLICE_X8Y51 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.612 -0.335
|
|
clock pessimism 0.037 -0.298
|
|
SLICE_X8Y51 FDCE (Hold_fdce_C_D) 0.120 -0.178 u_confreg/u_int_ctrl/edge_int_state_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 0.178
|
|
arrival time -0.117
|
|
-------------------------------------------------------------------
|
|
slack 0.061
|
|
|
|
Slack (MET) : 0.074ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.526ns (logic 0.210ns (39.912%) route 0.316ns (60.088%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.345ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.294ns
|
|
Source Clock Delay (SCD): -0.602ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.246 -0.602
|
|
SLICE_X112Y53 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C
|
|
SLICE_X112Y53 FDRE (Prop_fdre_C_Q) 0.164 -0.438 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/Q
|
|
net (fo=5, routed) 0.316 -0.122 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[10]
|
|
SLICE_X114Y49 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/I2
|
|
SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.046 -0.076 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/O
|
|
net (fo=1, routed) 0.000 -0.076 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[10]
|
|
SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.653 -0.294
|
|
clock pessimism 0.037 -0.257
|
|
SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.150
|
|
arrival time -0.076
|
|
-------------------------------------------------------------------
|
|
slack 0.074
|
|
|
|
Slack (MET) : 0.074ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.526ns (logic 0.210ns (39.912%) route 0.316ns (60.088%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.345ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.294ns
|
|
Source Clock Delay (SCD): -0.602ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.246 -0.602
|
|
SLICE_X112Y53 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C
|
|
SLICE_X112Y53 FDRE (Prop_fdre_C_Q) 0.164 -0.438 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/Q
|
|
net (fo=5, routed) 0.316 -0.122 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[10]
|
|
SLICE_X114Y49 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/I2
|
|
SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.046 -0.076 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/O
|
|
net (fo=1, routed) 0.000 -0.076 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[10]
|
|
SLICE_X114Y49 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.653 -0.294
|
|
clock pessimism 0.037 -0.257
|
|
SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.150
|
|
arrival time -0.076
|
|
-------------------------------------------------------------------
|
|
slack 0.074
|
|
|
|
Slack (MET) : 0.076ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.041ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.313ns
|
|
Source Clock Delay (SCD): -0.546ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.302 -0.546
|
|
SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q
|
|
net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1
|
|
SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.634 -0.313
|
|
clock pessimism -0.192 -0.505
|
|
SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.120
|
|
-------------------------------------------------------------------
|
|
slack 0.076
|
|
|
|
Slack (MET) : 0.076ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.041ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.313ns
|
|
Source Clock Delay (SCD): -0.546ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.302 -0.546
|
|
SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q
|
|
net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1
|
|
SLICE_X2Y66 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.634 -0.313
|
|
clock pessimism -0.192 -0.505
|
|
SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.120
|
|
-------------------------------------------------------------------
|
|
slack 0.076
|
|
|
|
Slack (MET) : 0.076ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.041ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.313ns
|
|
Source Clock Delay (SCD): -0.546ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.302 -0.546
|
|
SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q
|
|
net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1
|
|
SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.634 -0.313
|
|
clock pessimism -0.192 -0.505
|
|
SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.120
|
|
-------------------------------------------------------------------
|
|
slack 0.076
|
|
|
|
Slack (MET) : 0.076ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.041ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.313ns
|
|
Source Clock Delay (SCD): -0.546ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.302 -0.546
|
|
SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q
|
|
net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1
|
|
SLICE_X2Y66 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.634 -0.313
|
|
clock pessimism -0.192 -0.505
|
|
SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.120
|
|
-------------------------------------------------------------------
|
|
slack 0.076
|
|
|
|
Slack (MET) : 0.084ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.349ns (logic 0.164ns (46.999%) route 0.185ns (53.001%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.195ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.506ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.343 -0.506
|
|
SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 r u_cpu/u_csr/csr_tlbidx_reg[26]/Q
|
|
net (fo=33, routed) 0.185 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7]
|
|
SLICE_X39Y52 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.600 -0.347
|
|
clock pessimism 0.037 -0.310
|
|
SLICE_X39Y52 FDRE (Hold_fdre_C_D) 0.070 -0.240 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]
|
|
-------------------------------------------------------------------
|
|
required time 0.240
|
|
arrival time -0.157
|
|
-------------------------------------------------------------------
|
|
slack 0.084
|
|
|
|
Slack (MET) : 0.084ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.349ns (logic 0.164ns (46.999%) route 0.185ns (53.001%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.195ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.506ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.343 -0.506
|
|
SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 f u_cpu/u_csr/csr_tlbidx_reg[26]/Q
|
|
net (fo=33, routed) 0.185 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7]
|
|
SLICE_X39Y52 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.600 -0.347
|
|
clock pessimism 0.037 -0.310
|
|
SLICE_X39Y52 FDRE (Hold_fdre_C_D) 0.070 -0.240 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]
|
|
-------------------------------------------------------------------
|
|
required time 0.240
|
|
arrival time -0.157
|
|
-------------------------------------------------------------------
|
|
slack 0.084
|
|
|
|
Slack (MET) : 0.084ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.339ns (logic 0.128ns (37.707%) route 0.211ns (62.293%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.378ns
|
|
Source Clock Delay (SCD): -0.536ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.313 -0.536
|
|
SLICE_X47Y47 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[5]/C
|
|
SLICE_X47Y47 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[5]/Q
|
|
net (fo=1, routed) 0.211 -0.196 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIC1
|
|
SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.569 -0.378
|
|
clock pessimism 0.037 -0.341
|
|
SLICE_X44Y51 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.061 -0.280 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.280
|
|
arrival time -0.196
|
|
-------------------------------------------------------------------
|
|
slack 0.084
|
|
|
|
Slack (MET) : 0.084ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.339ns (logic 0.128ns (37.707%) route 0.211ns (62.293%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.378ns
|
|
Source Clock Delay (SCD): -0.536ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.313 -0.536
|
|
SLICE_X47Y47 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[5]/C
|
|
SLICE_X47Y47 FDRE (Prop_fdre_C_Q) 0.128 -0.408 f u_cpu/axi_bridge/araddr_reg[5]/Q
|
|
net (fo=1, routed) 0.211 -0.196 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIC1
|
|
SLICE_X44Y51 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.569 -0.378
|
|
clock pessimism 0.037 -0.341
|
|
SLICE_X44Y51 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.061 -0.280 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.280
|
|
arrival time -0.196
|
|
-------------------------------------------------------------------
|
|
slack 0.084
|
|
|
|
Slack (MET) : 0.084ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wstrb_reg[2]/C
|
|
(rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.187ns (logic 0.128ns (68.397%) route 0.059ns (31.603%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.496ns
|
|
Clock Pessimism Removal (CPR): 0.221ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.353 -0.496
|
|
SLICE_X15Y41 FDSE 0.000 -0.496 r u_cpu/axi_bridge/wstrb_reg[2]/C
|
|
SLICE_X15Y41 FDSE (Prop_fdse_C_Q) 0.128 -0.368 r u_cpu/axi_bridge/wstrb_reg[2]/Q
|
|
net (fo=1, routed) 0.059 -0.309 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIC0
|
|
SLICE_X14Y41 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.221 -0.483
|
|
SLICE_X14Y41 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.090 -0.393 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.393
|
|
arrival time -0.309
|
|
-------------------------------------------------------------------
|
|
slack 0.084
|
|
|
|
Slack (MET) : 0.084ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wstrb_reg[2]/C
|
|
(rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.187ns (logic 0.128ns (68.397%) route 0.059ns (31.603%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.496ns
|
|
Clock Pessimism Removal (CPR): 0.221ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.353 -0.496
|
|
SLICE_X15Y41 FDSE 0.000 -0.496 r u_cpu/axi_bridge/wstrb_reg[2]/C
|
|
SLICE_X15Y41 FDSE (Prop_fdse_C_Q) 0.128 -0.368 f u_cpu/axi_bridge/wstrb_reg[2]/Q
|
|
net (fo=1, routed) 0.059 -0.309 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIC0
|
|
SLICE_X14Y41 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.221 -0.483
|
|
SLICE_X14Y41 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.090 -0.393 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.393
|
|
arrival time -0.309
|
|
-------------------------------------------------------------------
|
|
slack 0.084
|
|
|
|
Slack (MET) : 0.086ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbidx_reg[27]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.347ns (logic 0.141ns (40.688%) route 0.206ns (59.312%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.346ns
|
|
Source Clock Delay (SCD): -0.504ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.345 -0.504
|
|
SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[27]/C
|
|
SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_tlbidx_reg[27]/Q
|
|
net (fo=33, routed) 0.206 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[8]
|
|
SLICE_X37Y50 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.601 -0.346
|
|
clock pessimism 0.037 -0.309
|
|
SLICE_X37Y50 FDRE (Hold_fdre_C_D) 0.066 -0.243 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]
|
|
-------------------------------------------------------------------
|
|
required time 0.243
|
|
arrival time -0.157
|
|
-------------------------------------------------------------------
|
|
slack 0.086
|
|
|
|
Slack (MET) : 0.086ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbidx_reg[27]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.347ns (logic 0.141ns (40.688%) route 0.206ns (59.312%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.346ns
|
|
Source Clock Delay (SCD): -0.504ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.345 -0.504
|
|
SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[27]/C
|
|
SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 f u_cpu/u_csr/csr_tlbidx_reg[27]/Q
|
|
net (fo=33, routed) 0.206 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[8]
|
|
SLICE_X37Y50 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.601 -0.346
|
|
clock pessimism 0.037 -0.309
|
|
SLICE_X37Y50 FDRE (Hold_fdre_C_D) 0.066 -0.243 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]
|
|
-------------------------------------------------------------------
|
|
required time 0.243
|
|
arrival time -0.157
|
|
-------------------------------------------------------------------
|
|
slack 0.086
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.569ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.279 -0.569
|
|
SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q
|
|
net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0
|
|
SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism -0.192 -0.531
|
|
SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.221
|
|
arrival time -0.135
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.569ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.279 -0.569
|
|
SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q
|
|
net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0
|
|
SLICE_X16Y61 RAMD32 f axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism -0.192 -0.531
|
|
SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.221
|
|
arrival time -0.135
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.569ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.279 -0.569
|
|
SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q
|
|
net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0
|
|
SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism -0.192 -0.531
|
|
SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.221
|
|
arrival time -0.135
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.569ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.279 -0.569
|
|
SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q
|
|
net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0
|
|
SLICE_X16Y61 RAMD32 f axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism -0.192 -0.531
|
|
SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.221
|
|
arrival time -0.135
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMS32 f u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0
|
|
SLICE_X48Y11 RAMS32 f u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.213
|
|
arrival time -0.126
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.230ns
|
|
Source Clock Delay (SCD): -0.466ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.383 -0.466
|
|
SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0
|
|
SLICE_X2Y46 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.717 -0.230
|
|
clock pessimism -0.220 -0.450
|
|
SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.140
|
|
arrival time -0.053
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q
|
|
net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1
|
|
SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1)
|
|
0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.196
|
|
arrival time -0.109
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.089ns (arrival time - required time)
|
|
Source: u_confreg/int_out_or_q1_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_confreg/int_out_or_q2_reg/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.480ns (logic 0.141ns (29.360%) route 0.339ns (70.640%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.316ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.260ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.309 -0.539
|
|
SLICE_X4Y50 FDRE 0.000 -0.539 r u_confreg/int_out_or_q1_reg/C
|
|
SLICE_X4Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/int_out_or_q1_reg/Q
|
|
net (fo=1, routed) 0.339 -0.059 u_confreg/int_out_or_q1
|
|
SLICE_X9Y47 FDRE r u_confreg/int_out_or_q2_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.687 -0.260
|
|
clock pessimism 0.037 -0.223
|
|
SLICE_X9Y47 FDRE (Hold_fdre_C_D) 0.075 -0.148 u_confreg/int_out_or_q2_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.148
|
|
arrival time -0.059
|
|
-------------------------------------------------------------------
|
|
slack 0.089
|
|
|
|
Slack (MET) : 0.089ns (arrival time - required time)
|
|
Source: u_confreg/int_out_or_q1_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_confreg/int_out_or_q2_reg/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.480ns (logic 0.141ns (29.360%) route 0.339ns (70.640%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.316ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.260ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.309 -0.539
|
|
SLICE_X4Y50 FDRE 0.000 -0.539 r u_confreg/int_out_or_q1_reg/C
|
|
SLICE_X4Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_confreg/int_out_or_q1_reg/Q
|
|
net (fo=1, routed) 0.339 -0.059 u_confreg/int_out_or_q1
|
|
SLICE_X9Y47 FDRE f u_confreg/int_out_or_q2_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.687 -0.260
|
|
clock pessimism 0.037 -0.223
|
|
SLICE_X9Y47 FDRE (Hold_fdre_C_D) 0.075 -0.148 u_confreg/int_out_or_q2_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.148
|
|
arrival time -0.059
|
|
-------------------------------------------------------------------
|
|
slack 0.089
|
|
|
|
Slack (MET) : 0.090ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[22]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.252ns (logic 0.141ns (55.979%) route 0.111ns (44.021%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.386ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
SLICE_X69Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[22]/C
|
|
SLICE_X69Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_cpu/u_csr/csr_tlbelo1_reg[22]/Q
|
|
net (fo=4, routed) 0.111 -0.363 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIB0
|
|
SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.561 -0.386
|
|
clock pessimism -0.213 -0.599
|
|
SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.453 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.453
|
|
arrival time -0.363
|
|
-------------------------------------------------------------------
|
|
slack 0.090
|
|
|
|
Slack (MET) : 0.090ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[22]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.252ns (logic 0.141ns (55.979%) route 0.111ns (44.021%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.386ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
SLICE_X69Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[22]/C
|
|
SLICE_X69Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_cpu/u_csr/csr_tlbelo1_reg[22]/Q
|
|
net (fo=4, routed) 0.111 -0.363 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIB0
|
|
SLICE_X66Y50 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.561 -0.386
|
|
clock pessimism -0.213 -0.599
|
|
SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.453 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.453
|
|
arrival time -0.363
|
|
-------------------------------------------------------------------
|
|
slack 0.090
|
|
|
|
Slack (MET) : 0.090ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.345ns (logic 0.128ns (37.132%) route 0.217ns (62.868%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.378ns
|
|
Source Clock Delay (SCD): -0.536ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.313 -0.536
|
|
SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[11]/C
|
|
SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[11]/Q
|
|
net (fo=1, routed) 0.217 -0.191 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC1
|
|
SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.569 -0.378
|
|
clock pessimism 0.037 -0.341
|
|
SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.060 -0.281 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.281
|
|
arrival time -0.191
|
|
-------------------------------------------------------------------
|
|
slack 0.090
|
|
|
|
Slack (MET) : 0.090ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.345ns (logic 0.128ns (37.132%) route 0.217ns (62.868%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.378ns
|
|
Source Clock Delay (SCD): -0.536ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.313 -0.536
|
|
SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[11]/C
|
|
SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 f u_cpu/axi_bridge/araddr_reg[11]/Q
|
|
net (fo=1, routed) 0.217 -0.191 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC1
|
|
SLICE_X44Y52 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.569 -0.378
|
|
clock pessimism 0.037 -0.341
|
|
SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.060 -0.281 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.281
|
|
arrival time -0.191
|
|
-------------------------------------------------------------------
|
|
slack 0.090
|
|
|
|
Slack (MET) : 0.093ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.358ns (logic 0.128ns (35.706%) route 0.230ns (64.294%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.378ns
|
|
Source Clock Delay (SCD): -0.536ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.313 -0.536
|
|
SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[9]/C
|
|
SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[9]/Q
|
|
net (fo=1, routed) 0.230 -0.177 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIB1
|
|
SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.569 -0.378
|
|
clock pessimism 0.037 -0.341
|
|
SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.071 -0.270 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.270
|
|
arrival time -0.177
|
|
-------------------------------------------------------------------
|
|
slack 0.093
|
|
|
|
Slack (MET) : 0.093ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[9]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.358ns (logic 0.128ns (35.706%) route 0.230ns (64.294%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.378ns
|
|
Source Clock Delay (SCD): -0.536ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.313 -0.536
|
|
SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[9]/C
|
|
SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 f u_cpu/axi_bridge/araddr_reg[9]/Q
|
|
net (fo=1, routed) 0.230 -0.177 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIB1
|
|
SLICE_X44Y52 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.569 -0.378
|
|
clock pessimism 0.037 -0.341
|
|
SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.071 -0.270 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.270
|
|
arrival time -0.177
|
|
-------------------------------------------------------------------
|
|
slack 0.093
|
|
|
|
Slack (MET) : 0.093ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6]
|
|
(rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.056ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): 0.212ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C
|
|
SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q
|
|
net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[2]
|
|
RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.601 -0.347
|
|
clock pessimism -0.212 -0.559
|
|
RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6])
|
|
0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.376
|
|
arrival time -0.283
|
|
-------------------------------------------------------------------
|
|
slack 0.093
|
|
|
|
Slack (MET) : 0.093ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6]
|
|
(rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.056ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): 0.212ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C
|
|
SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q
|
|
net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[2]
|
|
RAMB18_X6Y27 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.601 -0.347
|
|
clock pessimism -0.212 -0.559
|
|
RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6])
|
|
0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.376
|
|
arrival time -0.283
|
|
-------------------------------------------------------------------
|
|
slack 0.093
|
|
|
|
Slack (MET) : 0.093ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6]
|
|
(rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.056ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): 0.212ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C
|
|
SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q
|
|
net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[2]
|
|
RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.601 -0.347
|
|
clock pessimism -0.212 -0.559
|
|
RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6])
|
|
0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.376
|
|
arrival time -0.283
|
|
-------------------------------------------------------------------
|
|
slack 0.093
|
|
|
|
Slack (MET) : 0.093ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6]
|
|
(rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.056ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): 0.212ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C
|
|
SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q
|
|
net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[2]
|
|
RAMB18_X6Y26 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.601 -0.347
|
|
clock pessimism -0.212 -0.559
|
|
RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6])
|
|
0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.376
|
|
arrival time -0.283
|
|
-------------------------------------------------------------------
|
|
slack 0.093
|
|
|
|
Slack (MET) : 0.094ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.251ns (logic 0.141ns (56.174%) route 0.110ns (43.826%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.496ns
|
|
Clock Pessimism Removal (CPR): 0.222ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.353 -0.496
|
|
SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C
|
|
SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 r u_cpu/axi_bridge/awaddr_reg[10]/Q
|
|
net (fo=1, routed) 0.110 -0.245 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0
|
|
SLICE_X16Y49 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.222 -0.483
|
|
SLICE_X16Y49 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.339
|
|
arrival time -0.245
|
|
-------------------------------------------------------------------
|
|
slack 0.094
|
|
|
|
Slack (MET) : 0.094ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.251ns (logic 0.141ns (56.174%) route 0.110ns (43.826%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.496ns
|
|
Clock Pessimism Removal (CPR): 0.222ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.353 -0.496
|
|
SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C
|
|
SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 f u_cpu/axi_bridge/awaddr_reg[10]/Q
|
|
net (fo=1, routed) 0.110 -0.245 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0
|
|
SLICE_X16Y49 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.222 -0.483
|
|
SLICE_X16Y49 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.339
|
|
arrival time -0.245
|
|
-------------------------------------------------------------------
|
|
slack 0.094
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMS32 f u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q
|
|
net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1
|
|
SLICE_X48Y10 RAMS32 f u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism -0.217 -0.523
|
|
SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1)
|
|
0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.214
|
|
arrival time -0.118
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.097ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.443ns (logic 0.141ns (31.804%) route 0.302ns (68.196%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.276ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.388ns
|
|
Source Clock Delay (SCD): -0.619ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.230 -0.619
|
|
SLICE_X157Y150 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C
|
|
SLICE_X157Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/Q
|
|
net (fo=14, routed) 0.302 -0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[13]
|
|
SLICE_X159Y138 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
clock pessimism 0.045 -0.343
|
|
SLICE_X159Y138 FDCE (Hold_fdce_C_D) 0.070 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 0.273
|
|
arrival time -0.176
|
|
-------------------------------------------------------------------
|
|
slack 0.097
|
|
|
|
Slack (MET) : 0.097ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.443ns (logic 0.141ns (31.804%) route 0.302ns (68.196%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.276ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.388ns
|
|
Source Clock Delay (SCD): -0.619ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.230 -0.619
|
|
SLICE_X157Y150 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C
|
|
SLICE_X157Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/Q
|
|
net (fo=14, routed) 0.302 -0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[13]
|
|
SLICE_X159Y138 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
clock pessimism 0.045 -0.343
|
|
SLICE_X159Y138 FDCE (Hold_fdce_C_D) 0.070 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 0.273
|
|
arrival time -0.176
|
|
-------------------------------------------------------------------
|
|
slack 0.097
|
|
|
|
Slack (MET) : 0.098ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.475ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C
|
|
SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q
|
|
net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0
|
|
SLICE_X87Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/I3
|
|
SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1_n_0
|
|
SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.472 -0.475
|
|
clock pessimism 0.040 -0.435
|
|
SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.092 -0.343 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]
|
|
-------------------------------------------------------------------
|
|
required time 0.343
|
|
arrival time -0.245
|
|
-------------------------------------------------------------------
|
|
slack 0.098
|
|
|
|
Slack (MET) : 0.098ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.475ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C
|
|
SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q
|
|
net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0
|
|
SLICE_X87Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/I3
|
|
SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1_n_0
|
|
SLICE_X87Y152 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.472 -0.475
|
|
clock pessimism 0.040 -0.435
|
|
SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.092 -0.343 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]
|
|
-------------------------------------------------------------------
|
|
required time 0.343
|
|
arrival time -0.245
|
|
-------------------------------------------------------------------
|
|
slack 0.098
|
|
|
|
Slack (MET) : 0.099ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.475ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C
|
|
SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q
|
|
net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0
|
|
SLICE_X87Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/I3
|
|
SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1_n_0
|
|
SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.472 -0.475
|
|
clock pessimism 0.040 -0.435
|
|
SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.091 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]
|
|
-------------------------------------------------------------------
|
|
required time 0.344
|
|
arrival time -0.245
|
|
-------------------------------------------------------------------
|
|
slack 0.099
|
|
|
|
Slack (MET) : 0.099ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.475ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C
|
|
SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q
|
|
net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0
|
|
SLICE_X87Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/I3
|
|
SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1_n_0
|
|
SLICE_X87Y152 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.472 -0.475
|
|
clock pessimism 0.040 -0.435
|
|
SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.091 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]
|
|
-------------------------------------------------------------------
|
|
required time 0.344
|
|
arrival time -0.245
|
|
-------------------------------------------------------------------
|
|
slack 0.099
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.366ns (logic 0.164ns (44.815%) route 0.202ns (55.185%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.196ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.346ns
|
|
Source Clock Delay (SCD): -0.506ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.343 -0.506
|
|
SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 r u_cpu/u_csr/csr_tlbidx_reg[26]/Q
|
|
net (fo=33, routed) 0.202 -0.140 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7]
|
|
SLICE_X37Y51 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.601 -0.346
|
|
clock pessimism 0.037 -0.309
|
|
SLICE_X37Y51 FDRE (Hold_fdre_C_D) 0.070 -0.239 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]
|
|
-------------------------------------------------------------------
|
|
required time 0.239
|
|
arrival time -0.140
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.366ns (logic 0.164ns (44.815%) route 0.202ns (55.185%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.196ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.346ns
|
|
Source Clock Delay (SCD): -0.506ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.343 -0.506
|
|
SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C
|
|
SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 f u_cpu/u_csr/csr_tlbidx_reg[26]/Q
|
|
net (fo=33, routed) 0.202 -0.140 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7]
|
|
SLICE_X37Y51 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.601 -0.346
|
|
clock pessimism 0.037 -0.309
|
|
SLICE_X37Y51 FDRE (Hold_fdre_C_D) 0.070 -0.239 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]
|
|
-------------------------------------------------------------------
|
|
required time 0.239
|
|
arrival time -0.140
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.100ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4
|
|
(rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.287ns
|
|
Source Clock Delay (SCD): -0.517ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.332 -0.517
|
|
SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C
|
|
SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q
|
|
net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4
|
|
SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.660 -0.287
|
|
clock pessimism -0.218 -0.505
|
|
SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4)
|
|
0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.205
|
|
-------------------------------------------------------------------
|
|
slack 0.100
|
|
|
|
Slack (MET) : 0.101ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/m_in_a_reg[1][28]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.496ns (logic 0.164ns (33.088%) route 0.332ns (66.911%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.336ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.379ns
|
|
Source Clock Delay (SCD): -0.675ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.173 -0.675
|
|
SLICE_X44Y105 FDRE 0.000 -0.675 r u_matmul_axi_slave/m_in_a_reg[1][28]/C
|
|
SLICE_X44Y105 FDRE (Prop_fdre_C_Q) 0.164 -0.511 r u_matmul_axi_slave/m_in_a_reg[1][28]/Q
|
|
net (fo=1, routed) 0.332 -0.179 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[28]
|
|
SLICE_X56Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.568 -0.379
|
|
clock pessimism 0.040 -0.339
|
|
SLICE_X56Y98 FDRE (Hold_fdre_C_D) 0.059 -0.280 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time 0.280
|
|
arrival time -0.179
|
|
-------------------------------------------------------------------
|
|
slack 0.101
|
|
|
|
Slack (MET) : 0.101ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/m_in_a_reg[1][28]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.496ns (logic 0.164ns (33.088%) route 0.332ns (66.911%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.336ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.379ns
|
|
Source Clock Delay (SCD): -0.675ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.173 -0.675
|
|
SLICE_X44Y105 FDRE 0.000 -0.675 r u_matmul_axi_slave/m_in_a_reg[1][28]/C
|
|
SLICE_X44Y105 FDRE (Prop_fdre_C_Q) 0.164 -0.511 f u_matmul_axi_slave/m_in_a_reg[1][28]/Q
|
|
net (fo=1, routed) 0.332 -0.179 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[28]
|
|
SLICE_X56Y98 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.568 -0.379
|
|
clock pessimism 0.040 -0.339
|
|
SLICE_X56Y98 FDRE (Hold_fdre_C_D) 0.059 -0.280 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time 0.280
|
|
arrival time -0.179
|
|
-------------------------------------------------------------------
|
|
slack 0.101
|
|
|
|
Slack (MET) : 0.103ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[4]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.286ns (logic 0.141ns (49.244%) route 0.145ns (50.756%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.304ns
|
|
Source Clock Delay (SCD): -0.537ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.312 -0.537
|
|
SLICE_X50Y43 FDRE 0.000 -0.537 r u_cpu/u_csr/csr_tlbelo0_reg[4]/C
|
|
SLICE_X50Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_cpu/u_csr/csr_tlbelo0_reg[4]/Q
|
|
net (fo=7, routed) 0.145 -0.250 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/D
|
|
SLICE_X48Y43 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.643 -0.304
|
|
clock pessimism -0.196 -0.500
|
|
SLICE_X48Y43 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.354 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.354
|
|
arrival time -0.250
|
|
-------------------------------------------------------------------
|
|
slack 0.103
|
|
|
|
Slack (MET) : 0.103ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[4]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.286ns (logic 0.141ns (49.244%) route 0.145ns (50.756%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.304ns
|
|
Source Clock Delay (SCD): -0.537ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.312 -0.537
|
|
SLICE_X50Y43 FDRE 0.000 -0.537 r u_cpu/u_csr/csr_tlbelo0_reg[4]/C
|
|
SLICE_X50Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.396 f u_cpu/u_csr/csr_tlbelo0_reg[4]/Q
|
|
net (fo=7, routed) 0.145 -0.250 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/D
|
|
SLICE_X48Y43 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.643 -0.304
|
|
clock pessimism -0.196 -0.500
|
|
SLICE_X48Y43 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.354 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.354
|
|
arrival time -0.250
|
|
-------------------------------------------------------------------
|
|
slack 0.103
|
|
|
|
Slack (MET) : 0.104ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.442ns (logic 0.141ns (31.876%) route 0.301ns (68.124%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.378ns
|
|
Source Clock Delay (SCD): -0.536ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.313 -0.536
|
|
SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[10]/C
|
|
SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_cpu/axi_bridge/araddr_reg[10]/Q
|
|
net (fo=1, routed) 0.301 -0.093 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC0
|
|
SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.569 -0.378
|
|
clock pessimism 0.037 -0.341
|
|
SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.197 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.197
|
|
arrival time -0.093
|
|
-------------------------------------------------------------------
|
|
slack 0.104
|
|
|
|
Slack (MET) : 0.104ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.442ns (logic 0.141ns (31.876%) route 0.301ns (68.124%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.378ns
|
|
Source Clock Delay (SCD): -0.536ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.313 -0.536
|
|
SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[10]/C
|
|
SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.395 f u_cpu/axi_bridge/araddr_reg[10]/Q
|
|
net (fo=1, routed) 0.301 -0.093 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC0
|
|
SLICE_X44Y52 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.569 -0.378
|
|
clock pessimism 0.037 -0.341
|
|
SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.197 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.197
|
|
arrival time -0.093
|
|
-------------------------------------------------------------------
|
|
slack 0.104
|
|
|
|
Slack (MET) : 0.104ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.451ns (logic 0.141ns (31.244%) route 0.310ns (68.756%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.387ns
|
|
Source Clock Delay (SCD): -0.619ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.230 -0.619
|
|
SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C
|
|
SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/Q
|
|
net (fo=15, routed) 0.310 -0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[18]
|
|
SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
clock pessimism 0.045 -0.342
|
|
SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.070 -0.272 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.168
|
|
-------------------------------------------------------------------
|
|
slack 0.104
|
|
|
|
Slack (MET) : 0.104ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.451ns (logic 0.141ns (31.244%) route 0.310ns (68.756%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.387ns
|
|
Source Clock Delay (SCD): -0.619ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.230 -0.619
|
|
SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C
|
|
SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/Q
|
|
net (fo=15, routed) 0.310 -0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[18]
|
|
SLICE_X159Y140 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
clock pessimism 0.045 -0.342
|
|
SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.070 -0.272 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.168
|
|
-------------------------------------------------------------------
|
|
slack 0.104
|
|
|
|
Slack (MET) : 0.106ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8]
|
|
(rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.056ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): 0.212ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C
|
|
SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q
|
|
net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[4]
|
|
RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.601 -0.347
|
|
clock pessimism -0.212 -0.559
|
|
RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8])
|
|
0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.376
|
|
arrival time -0.270
|
|
-------------------------------------------------------------------
|
|
slack 0.106
|
|
|
|
Slack (MET) : 0.106ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8]
|
|
(rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.056ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): 0.212ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C
|
|
SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q
|
|
net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[4]
|
|
RAMB18_X6Y27 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.601 -0.347
|
|
clock pessimism -0.212 -0.559
|
|
RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8])
|
|
0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.376
|
|
arrival time -0.270
|
|
-------------------------------------------------------------------
|
|
slack 0.106
|
|
|
|
Slack (MET) : 0.106ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8]
|
|
(rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.056ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): 0.212ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C
|
|
SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q
|
|
net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[4]
|
|
RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.601 -0.347
|
|
clock pessimism -0.212 -0.559
|
|
RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8])
|
|
0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.376
|
|
arrival time -0.270
|
|
-------------------------------------------------------------------
|
|
slack 0.106
|
|
|
|
Slack (MET) : 0.106ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8]
|
|
(rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.056ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): 0.212ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C
|
|
SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q
|
|
net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[4]
|
|
RAMB18_X6Y26 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.601 -0.347
|
|
clock pessimism -0.212 -0.559
|
|
RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8])
|
|
0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.376
|
|
arrival time -0.270
|
|
-------------------------------------------------------------------
|
|
slack 0.106
|
|
|
|
Slack (MET) : 0.106ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.449ns (logic 0.141ns (31.381%) route 0.308ns (68.619%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.387ns
|
|
Source Clock Delay (SCD): -0.619ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.230 -0.619
|
|
SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C
|
|
SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/Q
|
|
net (fo=15, routed) 0.308 -0.170 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[17]
|
|
SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
clock pessimism 0.045 -0.342
|
|
SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.066 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]
|
|
-------------------------------------------------------------------
|
|
required time 0.276
|
|
arrival time -0.170
|
|
-------------------------------------------------------------------
|
|
slack 0.106
|
|
|
|
Slack (MET) : 0.106ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.449ns (logic 0.141ns (31.381%) route 0.308ns (68.619%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.387ns
|
|
Source Clock Delay (SCD): -0.619ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.230 -0.619
|
|
SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C
|
|
SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/Q
|
|
net (fo=15, routed) 0.308 -0.170 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[17]
|
|
SLICE_X159Y140 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
clock pessimism 0.045 -0.342
|
|
SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.066 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]
|
|
-------------------------------------------------------------------
|
|
required time 0.276
|
|
arrival time -0.170
|
|
-------------------------------------------------------------------
|
|
slack 0.106
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_confreg/buf_addr_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.425ns (logic 0.186ns (43.780%) route 0.239ns (56.220%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.195ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.336ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X13Y45 FDRE 0.000 -0.495 r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C
|
|
SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.354 r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/Q
|
|
net (fo=13, routed) 0.239 -0.115 u_Axi_CDC/arFifo/_zz_ram_port1[2]
|
|
SLICE_X16Y51 r u_Axi_CDC/arFifo/buf_addr[2]_i_1/I1
|
|
SLICE_X16Y51 LUT5 (Prop_lut5_I1_O) 0.045 -0.070 r u_Axi_CDC/arFifo/buf_addr[2]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.070 u_confreg/buf_addr_reg[15]_0[2]
|
|
SLICE_X16Y51 FDRE r u_confreg/buf_addr_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.611 -0.336
|
|
clock pessimism 0.037 -0.299
|
|
SLICE_X16Y51 FDRE (Hold_fdre_C_D) 0.121 -0.178 u_confreg/buf_addr_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.178
|
|
arrival time -0.070
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_confreg/buf_addr_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.425ns (logic 0.186ns (43.780%) route 0.239ns (56.220%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.195ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.336ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X13Y45 FDRE 0.000 -0.495 r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C
|
|
SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.354 f u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/Q
|
|
net (fo=13, routed) 0.239 -0.115 u_Axi_CDC/arFifo/_zz_ram_port1[2]
|
|
SLICE_X16Y51 f u_Axi_CDC/arFifo/buf_addr[2]_i_1/I1
|
|
SLICE_X16Y51 LUT5 (Prop_lut5_I1_O) 0.045 -0.070 f u_Axi_CDC/arFifo/buf_addr[2]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.070 u_confreg/buf_addr_reg[15]_0[2]
|
|
SLICE_X16Y51 FDRE f u_confreg/buf_addr_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.611 -0.336
|
|
clock pessimism 0.037 -0.299
|
|
SLICE_X16Y51 FDRE (Hold_fdre_C_D) 0.121 -0.178 u_confreg/buf_addr_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.178
|
|
arrival time -0.070
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.111ns (arrival time - required time)
|
|
Source: u_confreg/digital_data_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.353ns (logic 0.141ns (39.954%) route 0.212ns (60.046%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.195ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X0Y49 FDRE 0.000 -0.465 r u_confreg/digital_data_reg[1]/C
|
|
SLICE_X0Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.324 r u_confreg/digital_data_reg[1]/Q
|
|
net (fo=2, routed) 0.212 -0.112 u_confreg/u_digitaltube_controller/dpy1_data_reg[3]_0[1]
|
|
SLICE_X0Y54 FDRE r u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism 0.037 -0.269
|
|
SLICE_X0Y54 FDRE (Hold_fdre_C_D) 0.047 -0.222 u_confreg/u_digitaltube_controller/dpy0_data_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.222
|
|
arrival time -0.112
|
|
-------------------------------------------------------------------
|
|
slack 0.111
|
|
|
|
Slack (MET) : 0.111ns (arrival time - required time)
|
|
Source: u_confreg/digital_data_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.353ns (logic 0.141ns (39.954%) route 0.212ns (60.046%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.195ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.306ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X0Y49 FDRE 0.000 -0.465 r u_confreg/digital_data_reg[1]/C
|
|
SLICE_X0Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.324 f u_confreg/digital_data_reg[1]/Q
|
|
net (fo=2, routed) 0.212 -0.112 u_confreg/u_digitaltube_controller/dpy1_data_reg[3]_0[1]
|
|
SLICE_X0Y54 FDRE f u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.641 -0.306
|
|
clock pessimism 0.037 -0.269
|
|
SLICE_X0Y54 FDRE (Hold_fdre_C_D) 0.047 -0.222 u_confreg/u_digitaltube_controller/dpy0_data_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.222
|
|
arrival time -0.112
|
|
-------------------------------------------------------------------
|
|
slack 0.111
|
|
|
|
Slack (MET) : 0.111ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.410ns (logic 0.209ns (50.949%) route 0.201ns (49.051%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.192ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.371ns
|
|
Source Clock Delay (SCD): -0.527ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.322 -0.527
|
|
SLICE_X116Y49 FDRE 0.000 -0.527 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C
|
|
SLICE_X116Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.363 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/Q
|
|
net (fo=5, routed) 0.201 -0.162 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[3]
|
|
SLICE_X118Y50 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/I2
|
|
SLICE_X118Y50 LUT3 (Prop_lut3_I2_O) 0.045 -0.117 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/O
|
|
net (fo=1, routed) 0.000 -0.117 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[3]
|
|
SLICE_X118Y50 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.576 -0.371
|
|
clock pessimism 0.037 -0.334
|
|
SLICE_X118Y50 FDRE (Hold_fdre_C_D) 0.107 -0.227 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.227
|
|
arrival time -0.117
|
|
-------------------------------------------------------------------
|
|
slack 0.111
|
|
|
|
Slack (MET) : 0.111ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.410ns (logic 0.209ns (50.949%) route 0.201ns (49.051%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.192ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.371ns
|
|
Source Clock Delay (SCD): -0.527ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.322 -0.527
|
|
SLICE_X116Y49 FDRE 0.000 -0.527 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C
|
|
SLICE_X116Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.363 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/Q
|
|
net (fo=5, routed) 0.201 -0.162 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[3]
|
|
SLICE_X118Y50 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/I2
|
|
SLICE_X118Y50 LUT3 (Prop_lut3_I2_O) 0.045 -0.117 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/O
|
|
net (fo=1, routed) 0.000 -0.117 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[3]
|
|
SLICE_X118Y50 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.576 -0.371
|
|
clock pessimism 0.037 -0.334
|
|
SLICE_X118Y50 FDRE (Hold_fdre_C_D) 0.107 -0.227 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.227
|
|
arrival time -0.117
|
|
-------------------------------------------------------------------
|
|
slack 0.111
|
|
|
|
Slack (MET) : 0.111ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbidx_reg[24]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.376ns (logic 0.141ns (37.453%) route 0.235ns (62.547%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.195ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.345ns
|
|
Source Clock Delay (SCD): -0.504ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.345 -0.504
|
|
SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[24]/C
|
|
SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_tlbidx_reg[24]/Q
|
|
net (fo=33, routed) 0.235 -0.127 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[5]
|
|
SLICE_X32Y53 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.602 -0.345
|
|
clock pessimism 0.037 -0.308
|
|
SLICE_X32Y53 FDRE (Hold_fdre_C_D) 0.070 -0.238 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]
|
|
-------------------------------------------------------------------
|
|
required time 0.238
|
|
arrival time -0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.111
|
|
|
|
Slack (MET) : 0.111ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbidx_reg[24]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.376ns (logic 0.141ns (37.453%) route 0.235ns (62.547%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.195ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.345ns
|
|
Source Clock Delay (SCD): -0.504ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.345 -0.504
|
|
SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[24]/C
|
|
SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 f u_cpu/u_csr/csr_tlbidx_reg[24]/Q
|
|
net (fo=33, routed) 0.235 -0.127 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[5]
|
|
SLICE_X32Y53 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.602 -0.345
|
|
clock pessimism 0.037 -0.308
|
|
SLICE_X32Y53 FDRE (Hold_fdre_C_D) 0.070 -0.238 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]
|
|
-------------------------------------------------------------------
|
|
required time 0.238
|
|
arrival time -0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.111
|
|
|
|
Slack (MET) : 0.112ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.428ns (logic 0.141ns (32.928%) route 0.287ns (67.072%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.261ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.490ns
|
|
Source Clock Delay (SCD): -0.711ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.138 -0.711
|
|
SLICE_X85Y171 FDCE 0.000 -0.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C
|
|
SLICE_X85Y171 FDCE (Prop_fdce_C_Q) 0.141 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/Q
|
|
net (fo=14, routed) 0.287 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[12]
|
|
SLICE_X81Y173 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.457 -0.490
|
|
clock pessimism 0.040 -0.450
|
|
SLICE_X81Y173 FDCE (Hold_fdce_C_D) 0.055 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 0.395
|
|
arrival time -0.283
|
|
-------------------------------------------------------------------
|
|
slack 0.112
|
|
|
|
Slack (MET) : 0.112ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.428ns (logic 0.141ns (32.928%) route 0.287ns (67.072%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.261ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.490ns
|
|
Source Clock Delay (SCD): -0.711ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.138 -0.711
|
|
SLICE_X85Y171 FDCE 0.000 -0.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C
|
|
SLICE_X85Y171 FDCE (Prop_fdce_C_Q) 0.141 -0.570 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/Q
|
|
net (fo=14, routed) 0.287 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[12]
|
|
SLICE_X81Y173 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.457 -0.490
|
|
clock pessimism 0.040 -0.450
|
|
SLICE_X81Y173 FDCE (Hold_fdce_C_D) 0.055 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 0.395
|
|
arrival time -0.283
|
|
-------------------------------------------------------------------
|
|
slack 0.112
|
|
|
|
Slack (MET) : 0.113ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.305ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0
|
|
SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.642 -0.305
|
|
clock pessimism -0.217 -0.522
|
|
SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.212
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.113
|
|
|
|
Slack (MET) : 0.113ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.305ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0
|
|
SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.642 -0.305
|
|
clock pessimism -0.217 -0.522
|
|
SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.212
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.113
|
|
|
|
Slack (MET) : 0.113ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.305ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0
|
|
SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.642 -0.305
|
|
clock pessimism -0.217 -0.522
|
|
SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.212
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.113
|
|
|
|
Slack (MET) : 0.113ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.305ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0
|
|
SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.642 -0.305
|
|
clock pessimism -0.217 -0.522
|
|
SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.212
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.113
|
|
|
|
Slack (MET) : 0.113ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.305ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0
|
|
SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.642 -0.305
|
|
clock pessimism -0.217 -0.522
|
|
SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.212
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.113
|
|
|
|
Slack (MET) : 0.113ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.305ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0
|
|
SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.642 -0.305
|
|
clock pessimism -0.217 -0.522
|
|
SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.212
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.113
|
|
|
|
Slack (MET) : 0.113ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.305ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0
|
|
SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.642 -0.305
|
|
clock pessimism -0.217 -0.522
|
|
SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.212
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.113
|
|
|
|
Slack (MET) : 0.113ns (arrival time - required time)
|
|
Source: u_cpu/btb/ras_ptr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.305ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.310 -0.539
|
|
SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C
|
|
SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q
|
|
net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0
|
|
SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.642 -0.305
|
|
clock pessimism -0.217 -0.522
|
|
SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.212
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.113
|
|
|
|
Slack (MET) : 0.114ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.488ns (logic 0.231ns (47.314%) route 0.257ns (52.686%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.267ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.399ns
|
|
Source Clock Delay (SCD): -0.629ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.219 -0.629
|
|
SLICE_X83Y93 FDCE 0.000 -0.629 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C
|
|
SLICE_X83Y93 FDCE (Prop_fdce_C_Q) 0.128 -0.501 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/Q
|
|
net (fo=118, routed) 0.257 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10_n_0
|
|
SLICE_X85Y98 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/I0
|
|
SLICE_X85Y98 LUT2 (Prop_lut2_I0_O) 0.103 -0.141 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1_n_0
|
|
SLICE_X85Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.548 -0.399
|
|
clock pessimism 0.037 -0.362
|
|
SLICE_X85Y98 FDCE (Hold_fdce_C_D) 0.107 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]
|
|
-------------------------------------------------------------------
|
|
required time 0.255
|
|
arrival time -0.141
|
|
-------------------------------------------------------------------
|
|
slack 0.114
|
|
|
|
Slack (MET) : 0.114ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.488ns (logic 0.231ns (47.314%) route 0.257ns (52.686%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.267ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.399ns
|
|
Source Clock Delay (SCD): -0.629ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.219 -0.629
|
|
SLICE_X83Y93 FDCE 0.000 -0.629 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C
|
|
SLICE_X83Y93 FDCE (Prop_fdce_C_Q) 0.128 -0.501 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/Q
|
|
net (fo=118, routed) 0.257 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10_n_0
|
|
SLICE_X85Y98 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/I0
|
|
SLICE_X85Y98 LUT2 (Prop_lut2_I0_O) 0.103 -0.141 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1_n_0
|
|
SLICE_X85Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.548 -0.399
|
|
clock pessimism 0.037 -0.362
|
|
SLICE_X85Y98 FDCE (Hold_fdce_C_D) 0.107 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]
|
|
-------------------------------------------------------------------
|
|
required time 0.255
|
|
arrival time -0.141
|
|
-------------------------------------------------------------------
|
|
slack 0.114
|
|
|
|
Slack (MET) : 0.115ns (arrival time - required time)
|
|
Source: u_confreg/confreg_int_edge_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.196ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.305ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C
|
|
SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 r u_confreg/confreg_int_edge_reg[3]/Q
|
|
net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3]
|
|
SLICE_X3Y50 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0
|
|
SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0
|
|
SLICE_X3Y50 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.642 -0.305
|
|
clock pessimism 0.037 -0.268
|
|
SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.177
|
|
arrival time -0.063
|
|
-------------------------------------------------------------------
|
|
slack 0.115
|
|
|
|
Slack (MET) : 0.115ns (arrival time - required time)
|
|
Source: u_confreg/confreg_int_edge_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.196ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.305ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C
|
|
SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 f u_confreg/confreg_int_edge_reg[3]/Q
|
|
net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3]
|
|
SLICE_X3Y50 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0
|
|
SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0
|
|
SLICE_X3Y50 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.642 -0.305
|
|
clock pessimism 0.037 -0.268
|
|
SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.177
|
|
arrival time -0.063
|
|
-------------------------------------------------------------------
|
|
slack 0.115
|
|
|
|
Slack (MET) : 0.115ns (arrival time - required time)
|
|
Source: u_confreg/confreg_int_edge_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.196ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.305ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C
|
|
SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 r u_confreg/confreg_int_edge_reg[3]/Q
|
|
net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3]
|
|
SLICE_X3Y50 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0
|
|
SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0
|
|
SLICE_X3Y50 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.642 -0.305
|
|
clock pessimism 0.037 -0.268
|
|
SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.177
|
|
arrival time -0.063
|
|
-------------------------------------------------------------------
|
|
slack 0.115
|
|
|
|
Slack (MET) : 0.115ns (arrival time - required time)
|
|
Source: u_confreg/confreg_int_edge_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.196ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.305ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C
|
|
SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 f u_confreg/confreg_int_edge_reg[3]/Q
|
|
net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3]
|
|
SLICE_X3Y50 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0
|
|
SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0
|
|
SLICE_X3Y50 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.642 -0.305
|
|
clock pessimism 0.037 -0.268
|
|
SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.177
|
|
arrival time -0.063
|
|
-------------------------------------------------------------------
|
|
slack 0.115
|
|
|
|
Slack (MET) : 0.115ns (arrival time - required time)
|
|
Source: u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.387ns (logic 0.141ns (36.445%) route 0.246ns (63.555%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.196ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.305ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X1Y49 FDCE 0.000 -0.465 r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C
|
|
SLICE_X1Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/Q
|
|
net (fo=3, routed) 0.246 -0.078 u_confreg/u_int_ctrl/int_in_sync_d2[5]
|
|
SLICE_X3Y51 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.642 -0.305
|
|
clock pessimism 0.037 -0.268
|
|
SLICE_X3Y51 FDCE (Hold_fdce_C_D) 0.075 -0.193 u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 0.193
|
|
arrival time -0.078
|
|
-------------------------------------------------------------------
|
|
slack 0.115
|
|
|
|
Slack (MET) : 0.115ns (arrival time - required time)
|
|
Source: u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.387ns (logic 0.141ns (36.445%) route 0.246ns (63.555%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.196ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.305ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X1Y49 FDCE 0.000 -0.465 r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C
|
|
SLICE_X1Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/Q
|
|
net (fo=3, routed) 0.246 -0.078 u_confreg/u_int_ctrl/int_in_sync_d2[5]
|
|
SLICE_X3Y51 FDCE f u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.642 -0.305
|
|
clock pessimism 0.037 -0.268
|
|
SLICE_X3Y51 FDCE (Hold_fdce_C_D) 0.075 -0.193 u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 0.193
|
|
arrival time -0.078
|
|
-------------------------------------------------------------------
|
|
slack 0.115
|
|
|
|
Slack (MET) : 0.116ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.465ns (logic 0.141ns (30.326%) route 0.324ns (69.674%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.387ns
|
|
Source Clock Delay (SCD): -0.619ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.230 -0.619
|
|
SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C
|
|
SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/Q
|
|
net (fo=15, routed) 0.324 -0.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[19]
|
|
SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
clock pessimism 0.045 -0.342
|
|
SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.072 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time 0.270
|
|
arrival time -0.154
|
|
-------------------------------------------------------------------
|
|
slack 0.116
|
|
|
|
Slack (MET) : 0.116ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.465ns (logic 0.141ns (30.326%) route 0.324ns (69.674%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.387ns
|
|
Source Clock Delay (SCD): -0.619ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.230 -0.619
|
|
SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C
|
|
SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/Q
|
|
net (fo=15, routed) 0.324 -0.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[19]
|
|
SLICE_X159Y140 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
clock pessimism 0.045 -0.342
|
|
SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.072 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time 0.270
|
|
arrival time -0.154
|
|
-------------------------------------------------------------------
|
|
slack 0.116
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMS32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.337ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0
|
|
SLICE_X16Y54 RAMS32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.610 -0.337
|
|
clock pessimism 0.037 -0.300
|
|
SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.118ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.209ns (44.013%) route 0.266ns (55.987%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.265ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.420ns
|
|
Source Clock Delay (SCD): -0.640ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.208 -0.640
|
|
SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C
|
|
SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q
|
|
net (fo=127, routed) 0.266 -0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0
|
|
SLICE_X151Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/I1
|
|
SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.165 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1_n_0
|
|
SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.527 -0.420
|
|
clock pessimism 0.045 -0.375
|
|
SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.092 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]
|
|
-------------------------------------------------------------------
|
|
required time 0.283
|
|
arrival time -0.165
|
|
-------------------------------------------------------------------
|
|
slack 0.118
|
|
|
|
Slack (MET) : 0.118ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.209ns (44.013%) route 0.266ns (55.987%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.265ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.420ns
|
|
Source Clock Delay (SCD): -0.640ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.208 -0.640
|
|
SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C
|
|
SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q
|
|
net (fo=127, routed) 0.266 -0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0
|
|
SLICE_X151Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/I1
|
|
SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.165 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1_n_0
|
|
SLICE_X151Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.527 -0.420
|
|
clock pessimism 0.045 -0.375
|
|
SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.092 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]
|
|
-------------------------------------------------------------------
|
|
required time 0.283
|
|
arrival time -0.165
|
|
-------------------------------------------------------------------
|
|
slack 0.118
|
|
|
|
Slack (MET) : 0.119ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.209ns (44.040%) route 0.266ns (55.960%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.403ns
|
|
Source Clock Delay (SCD): -0.630ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.218 -0.630
|
|
SLICE_X84Y61 FDRE 0.000 -0.630 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C
|
|
SLICE_X84Y61 FDRE (Prop_fdre_C_Q) 0.164 -0.466 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/Q
|
|
net (fo=6, routed) 0.266 -0.201 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][14]__0_0[7]
|
|
SLICE_X82Y61 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/I3
|
|
SLICE_X82Y61 LUT6 (Prop_lut6_I3_O) 0.045 -0.156 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.156 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_sp_re[7]
|
|
SLICE_X82Y61 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.544 -0.403
|
|
clock pessimism 0.037 -0.366
|
|
SLICE_X82Y61 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 0.274
|
|
arrival time -0.156
|
|
-------------------------------------------------------------------
|
|
slack 0.119
|
|
|
|
Slack (MET) : 0.119ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.209ns (44.040%) route 0.266ns (55.960%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.403ns
|
|
Source Clock Delay (SCD): -0.630ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.218 -0.630
|
|
SLICE_X84Y61 FDRE 0.000 -0.630 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C
|
|
SLICE_X84Y61 FDRE (Prop_fdre_C_Q) 0.164 -0.466 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/Q
|
|
net (fo=6, routed) 0.266 -0.201 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][14]__0_0[7]
|
|
SLICE_X82Y61 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/I3
|
|
SLICE_X82Y61 LUT6 (Prop_lut6_I3_O) 0.045 -0.156 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.156 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_sp_re[7]
|
|
SLICE_X82Y61 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.544 -0.403
|
|
clock pessimism 0.037 -0.366
|
|
SLICE_X82Y61 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 0.274
|
|
arrival time -0.156
|
|
-------------------------------------------------------------------
|
|
slack 0.119
|
|
|
|
Slack (MET) : 0.119ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.418ns
|
|
Source Clock Delay (SCD): -0.645ns
|
|
Clock Pessimism Removal (CPR): 0.227ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.203 -0.645
|
|
SLICE_X39Y105 FDRE 0.000 -0.645 r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C
|
|
SLICE_X39Y105 FDRE (Prop_fdre_C_Q) 0.141 -0.504 r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/Q
|
|
net (fo=1, routed) 0.056 -0.448 u_matmul_axi_slave/mult_inst[3].u_mult/prod[59]
|
|
SLICE_X39Y105 FDRE r u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.529 -0.418
|
|
clock pessimism -0.227 -0.645
|
|
SLICE_X39Y105 FDRE (Hold_fdre_C_D) 0.078 -0.567 u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]
|
|
-------------------------------------------------------------------
|
|
required time 0.567
|
|
arrival time -0.448
|
|
-------------------------------------------------------------------
|
|
slack 0.119
|
|
|
|
Slack (MET) : 0.119ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.418ns
|
|
Source Clock Delay (SCD): -0.645ns
|
|
Clock Pessimism Removal (CPR): 0.227ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.203 -0.645
|
|
SLICE_X39Y105 FDRE 0.000 -0.645 r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C
|
|
SLICE_X39Y105 FDRE (Prop_fdre_C_Q) 0.141 -0.504 f u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/Q
|
|
net (fo=1, routed) 0.056 -0.448 u_matmul_axi_slave/mult_inst[3].u_mult/prod[59]
|
|
SLICE_X39Y105 FDRE f u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.529 -0.418
|
|
clock pessimism -0.227 -0.645
|
|
SLICE_X39Y105 FDRE (Hold_fdre_C_D) 0.078 -0.567 u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]
|
|
-------------------------------------------------------------------
|
|
required time 0.567
|
|
arrival time -0.448
|
|
-------------------------------------------------------------------
|
|
slack 0.119
|
|
|
|
Slack (MET) : 0.120ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.476ns (logic 0.209ns (43.921%) route 0.267ns (56.079%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.265ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.420ns
|
|
Source Clock Delay (SCD): -0.640ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.208 -0.640
|
|
SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C
|
|
SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q
|
|
net (fo=127, routed) 0.267 -0.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0
|
|
SLICE_X151Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/I1
|
|
SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.164 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1_n_0
|
|
SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.527 -0.420
|
|
clock pessimism 0.045 -0.375
|
|
SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.091 -0.284 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]
|
|
-------------------------------------------------------------------
|
|
required time 0.284
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.120
|
|
|
|
Slack (MET) : 0.120ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.476ns (logic 0.209ns (43.921%) route 0.267ns (56.079%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.265ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.420ns
|
|
Source Clock Delay (SCD): -0.640ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.208 -0.640
|
|
SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C
|
|
SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q
|
|
net (fo=127, routed) 0.267 -0.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0
|
|
SLICE_X151Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/I1
|
|
SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1_n_0
|
|
SLICE_X151Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.527 -0.420
|
|
clock pessimism 0.045 -0.375
|
|
SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.091 -0.284 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]
|
|
-------------------------------------------------------------------
|
|
required time 0.284
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.120
|
|
|
|
Slack (MET) : 0.727ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.651ns (logic 0.227ns (34.873%) route 0.424ns (65.127%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.263ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.143 0.154 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X11Y39 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.684 -0.263
|
|
clock pessimism -0.218 -0.481
|
|
SLICE_X11Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.573 u_Axi_CDC/bFifo/popCC_popPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.573
|
|
arrival time 0.154
|
|
-------------------------------------------------------------------
|
|
slack 0.727
|
|
|
|
Slack (MET) : 0.727ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.651ns (logic 0.227ns (34.873%) route 0.424ns (65.127%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.263ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.143 0.154 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X11Y39 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.684 -0.263
|
|
clock pessimism -0.218 -0.481
|
|
SLICE_X11Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.573 u_Axi_CDC/bFifo/popCC_popPtr_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.573
|
|
arrival time 0.154
|
|
-------------------------------------------------------------------
|
|
slack 0.727
|
|
|
|
Slack (MET) : 0.761ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.525
|
|
arrival time 0.236
|
|
-------------------------------------------------------------------
|
|
slack 0.761
|
|
|
|
Slack (MET) : 0.761ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.525
|
|
arrival time 0.236
|
|
-------------------------------------------------------------------
|
|
slack 0.761
|
|
|
|
Slack (MET) : 0.761ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.525
|
|
arrival time 0.236
|
|
-------------------------------------------------------------------
|
|
slack 0.761
|
|
|
|
Slack (MET) : 0.761ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.525
|
|
arrival time 0.236
|
|
-------------------------------------------------------------------
|
|
slack 0.761
|
|
|
|
Slack (MET) : 0.765ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.218 -0.480
|
|
SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.547
|
|
arrival time 0.218
|
|
-------------------------------------------------------------------
|
|
slack 0.765
|
|
|
|
Slack (MET) : 0.765ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.218 -0.480
|
|
SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.547
|
|
arrival time 0.218
|
|
-------------------------------------------------------------------
|
|
slack 0.765
|
|
|
|
Slack (MET) : 0.765ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.218 -0.480
|
|
SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.547
|
|
arrival time 0.218
|
|
-------------------------------------------------------------------
|
|
slack 0.765
|
|
|
|
Slack (MET) : 0.765ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.218 -0.480
|
|
SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.547
|
|
arrival time 0.218
|
|
-------------------------------------------------------------------
|
|
slack 0.765
|
|
|
|
Slack (MET) : 0.765ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.218 -0.480
|
|
SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.547
|
|
arrival time 0.218
|
|
-------------------------------------------------------------------
|
|
slack 0.765
|
|
|
|
Slack (MET) : 0.765ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.218 -0.480
|
|
SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.547
|
|
arrival time 0.218
|
|
-------------------------------------------------------------------
|
|
slack 0.765
|
|
|
|
Slack (MET) : 0.790ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.736ns (logic 0.227ns (30.836%) route 0.509ns (69.164%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.263ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.228 0.239 u_Axi_CDC/rFifo/buffers_0_reg[3]
|
|
SLICE_X13Y39 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.684 -0.263
|
|
clock pessimism -0.196 -0.459
|
|
SLICE_X13Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.551 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.551
|
|
arrival time 0.239
|
|
-------------------------------------------------------------------
|
|
slack 0.790
|
|
|
|
Slack (MET) : 0.790ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.218 -0.480
|
|
SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.572
|
|
arrival time 0.218
|
|
-------------------------------------------------------------------
|
|
slack 0.790
|
|
|
|
Slack (MET) : 0.790ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.218 -0.480
|
|
SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_popPtr_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.572
|
|
arrival time 0.218
|
|
-------------------------------------------------------------------
|
|
slack 0.790
|
|
|
|
Slack (MET) : 0.790ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.218 -0.480
|
|
SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.572
|
|
arrival time 0.218
|
|
-------------------------------------------------------------------
|
|
slack 0.790
|
|
|
|
Slack (MET) : 0.790ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.218 -0.480
|
|
SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.572
|
|
arrival time 0.218
|
|
-------------------------------------------------------------------
|
|
slack 0.790
|
|
|
|
Slack (MET) : 0.790ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.218 -0.480
|
|
SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.572
|
|
arrival time 0.218
|
|
-------------------------------------------------------------------
|
|
slack 0.790
|
|
|
|
Slack (MET) : 0.808ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.221ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.221 -0.482
|
|
SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.574
|
|
arrival time 0.234
|
|
-------------------------------------------------------------------
|
|
slack 0.808
|
|
|
|
Slack (MET) : 0.808ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.221ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.221 -0.482
|
|
SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.574
|
|
arrival time 0.234
|
|
-------------------------------------------------------------------
|
|
slack 0.808
|
|
|
|
Slack (MET) : 0.808ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.221ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.221 -0.482
|
|
SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.574
|
|
arrival time 0.234
|
|
-------------------------------------------------------------------
|
|
slack 0.808
|
|
|
|
Slack (MET) : 0.808ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.221ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.221 -0.482
|
|
SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.574
|
|
arrival time 0.234
|
|
-------------------------------------------------------------------
|
|
slack 0.808
|
|
|
|
Slack (MET) : 0.808ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.221ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.221 -0.482
|
|
SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.574
|
|
arrival time 0.234
|
|
-------------------------------------------------------------------
|
|
slack 0.808
|
|
|
|
Slack (MET) : 0.808ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.221ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.221 -0.482
|
|
SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.574
|
|
arrival time 0.234
|
|
-------------------------------------------------------------------
|
|
slack 0.808
|
|
|
|
Slack (MET) : 0.853ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in
|
|
SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.196 -0.457
|
|
SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.524
|
|
arrival time 0.329
|
|
-------------------------------------------------------------------
|
|
slack 0.853
|
|
|
|
Slack (MET) : 0.853ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in
|
|
SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.196 -0.457
|
|
SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.524
|
|
arrival time 0.329
|
|
-------------------------------------------------------------------
|
|
slack 0.853
|
|
|
|
Slack (MET) : 0.853ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in
|
|
SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.196 -0.457
|
|
SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.524
|
|
arrival time 0.329
|
|
-------------------------------------------------------------------
|
|
slack 0.853
|
|
|
|
Slack (MET) : 0.853ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in
|
|
SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.196 -0.457
|
|
SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.524
|
|
arrival time 0.329
|
|
-------------------------------------------------------------------
|
|
slack 0.853
|
|
|
|
Slack (MET) : 0.853ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in
|
|
SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.196 -0.457
|
|
SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.524
|
|
arrival time 0.329
|
|
-------------------------------------------------------------------
|
|
slack 0.853
|
|
|
|
Slack (MET) : 0.860ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.550
|
|
arrival time 0.310
|
|
-------------------------------------------------------------------
|
|
slack 0.860
|
|
|
|
Slack (MET) : 0.860ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.550
|
|
arrival time 0.310
|
|
-------------------------------------------------------------------
|
|
slack 0.860
|
|
|
|
Slack (MET) : 0.860ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.550
|
|
arrival time 0.310
|
|
-------------------------------------------------------------------
|
|
slack 0.860
|
|
|
|
Slack (MET) : 0.860ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.550
|
|
arrival time 0.310
|
|
-------------------------------------------------------------------
|
|
slack 0.860
|
|
|
|
Slack (MET) : 0.871ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.794ns (logic 0.246ns (30.972%) route 0.548ns (69.028%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.262 0.299 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X9Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.218 -0.480
|
|
SLICE_X9Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.572
|
|
arrival time 0.299
|
|
-------------------------------------------------------------------
|
|
slack 0.871
|
|
|
|
Slack (MET) : 0.871ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.794ns (logic 0.246ns (30.972%) route 0.548ns (69.028%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.262 0.299 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X9Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.218 -0.480
|
|
SLICE_X9Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.572
|
|
arrival time 0.299
|
|
-------------------------------------------------------------------
|
|
slack 0.871
|
|
|
|
Slack (MET) : 0.872ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg
|
|
SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.218 -0.479
|
|
SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.571
|
|
arrival time 0.301
|
|
-------------------------------------------------------------------
|
|
slack 0.872
|
|
|
|
Slack (MET) : 0.872ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg
|
|
SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.218 -0.479
|
|
SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.571
|
|
arrival time 0.301
|
|
-------------------------------------------------------------------
|
|
slack 0.872
|
|
|
|
Slack (MET) : 0.872ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg
|
|
SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.218 -0.479
|
|
SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.571
|
|
arrival time 0.301
|
|
-------------------------------------------------------------------
|
|
slack 0.872
|
|
|
|
Slack (MET) : 0.890ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.864ns (logic 0.186ns (21.517%) route 0.678ns (78.483%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.041ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.380ns
|
|
Source Clock Delay (SCD): -0.613ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0
|
|
SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O
|
|
net (fo=5108, routed) 0.372 0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in
|
|
SLICE_X112Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.567 -0.380
|
|
clock pessimism -0.192 -0.572
|
|
SLICE_X112Y66 FDCE (Remov_fdce_C_CLR) -0.067 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.639
|
|
arrival time 0.251
|
|
-------------------------------------------------------------------
|
|
slack 0.890
|
|
|
|
Slack (MET) : 0.914ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.786ns (logic 0.249ns (31.687%) route 0.537ns (68.313%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.377ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.371 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X125Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.570 -0.377
|
|
clock pessimism -0.192 -0.569
|
|
SLICE_X125Y65 FDCE (Remov_fdce_C_CLR) -0.165 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]
|
|
-------------------------------------------------------------------
|
|
required time 0.734
|
|
arrival time 0.179
|
|
-------------------------------------------------------------------
|
|
slack 0.914
|
|
|
|
Slack (MET) : 0.917ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.010ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.525
|
|
arrival time 0.392
|
|
-------------------------------------------------------------------
|
|
slack 0.917
|
|
|
|
Slack (MET) : 0.917ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.010ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.525
|
|
arrival time 0.392
|
|
-------------------------------------------------------------------
|
|
slack 0.917
|
|
|
|
Slack (MET) : 0.917ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.010ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.525
|
|
arrival time 0.392
|
|
-------------------------------------------------------------------
|
|
slack 0.917
|
|
|
|
Slack (MET) : 0.917ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.010ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.525
|
|
arrival time 0.392
|
|
-------------------------------------------------------------------
|
|
slack 0.917
|
|
|
|
Slack (MET) : 0.917ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.010ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.525
|
|
arrival time 0.392
|
|
-------------------------------------------------------------------
|
|
slack 0.917
|
|
|
|
Slack (MET) : 0.917ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.010ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.525
|
|
arrival time 0.392
|
|
-------------------------------------------------------------------
|
|
slack 0.917
|
|
|
|
Slack (MET) : 0.917ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.010ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.525
|
|
arrival time 0.392
|
|
-------------------------------------------------------------------
|
|
slack 0.917
|
|
|
|
Slack (MET) : 0.917ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.010ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.525
|
|
arrival time 0.392
|
|
-------------------------------------------------------------------
|
|
slack 0.917
|
|
|
|
Slack (MET) : 0.917ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.040ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3]
|
|
SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.196 -0.457
|
|
SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.549
|
|
arrival time 0.368
|
|
-------------------------------------------------------------------
|
|
slack 0.917
|
|
|
|
Slack (MET) : 0.917ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.040ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3]
|
|
SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.196 -0.457
|
|
SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.549
|
|
arrival time 0.368
|
|
-------------------------------------------------------------------
|
|
slack 0.917
|
|
|
|
Slack (MET) : 0.917ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.040ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3]
|
|
SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.196 -0.457
|
|
SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.549
|
|
arrival time 0.368
|
|
-------------------------------------------------------------------
|
|
slack 0.917
|
|
|
|
Slack (MET) : 0.917ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.040ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3]
|
|
SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.196 -0.457
|
|
SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.549
|
|
arrival time 0.368
|
|
-------------------------------------------------------------------
|
|
slack 0.917
|
|
|
|
Slack (MET) : 0.918ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.021ns (logic 0.246ns (24.092%) route 0.775ns (75.908%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.195ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.336ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.489 0.526 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X11Y53 FDCE f u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.611 -0.336
|
|
clock pessimism 0.037 -0.299
|
|
SLICE_X11Y53 FDCE (Remov_fdce_C_CLR) -0.092 -0.391 u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.391
|
|
arrival time 0.526
|
|
-------------------------------------------------------------------
|
|
slack 0.918
|
|
|
|
Slack (MET) : 0.928ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg
|
|
SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.218 -0.479
|
|
SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.571
|
|
arrival time 0.357
|
|
-------------------------------------------------------------------
|
|
slack 0.928
|
|
|
|
Slack (MET) : 0.928ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg
|
|
SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.218 -0.479
|
|
SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.571
|
|
arrival time 0.357
|
|
-------------------------------------------------------------------
|
|
slack 0.928
|
|
|
|
Slack (MET) : 0.928ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg
|
|
SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.218 -0.479
|
|
SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.571
|
|
arrival time 0.357
|
|
-------------------------------------------------------------------
|
|
slack 0.928
|
|
|
|
Slack (MET) : 0.928ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg
|
|
SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.218 -0.479
|
|
SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.571
|
|
arrival time 0.357
|
|
-------------------------------------------------------------------
|
|
slack 0.928
|
|
|
|
Slack (MET) : 0.932ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.817ns (logic 0.249ns (30.489%) route 0.568ns (69.511%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.389ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.402 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X112Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
clock pessimism -0.192 -0.581
|
|
SLICE_X112Y75 FDCE (Remov_fdce_C_CLR) -0.140 -0.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.721
|
|
arrival time 0.210
|
|
-------------------------------------------------------------------
|
|
slack 0.932
|
|
|
|
Slack (MET) : 0.935ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.042ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.379ns
|
|
Source Clock Delay (SCD): -0.613ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0
|
|
SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O
|
|
net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in
|
|
SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.568 -0.379
|
|
clock pessimism -0.192 -0.571
|
|
SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.638
|
|
arrival time 0.297
|
|
-------------------------------------------------------------------
|
|
slack 0.935
|
|
|
|
Slack (MET) : 0.935ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.042ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.379ns
|
|
Source Clock Delay (SCD): -0.613ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0
|
|
SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O
|
|
net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in
|
|
SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.568 -0.379
|
|
clock pessimism -0.192 -0.571
|
|
SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.638
|
|
arrival time 0.297
|
|
-------------------------------------------------------------------
|
|
slack 0.935
|
|
|
|
Slack (MET) : 0.935ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.042ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.379ns
|
|
Source Clock Delay (SCD): -0.613ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0
|
|
SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O
|
|
net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in
|
|
SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.568 -0.379
|
|
clock pessimism -0.192 -0.571
|
|
SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.638
|
|
arrival time 0.297
|
|
-------------------------------------------------------------------
|
|
slack 0.935
|
|
|
|
Slack (MET) : 0.935ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.042ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.379ns
|
|
Source Clock Delay (SCD): -0.613ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0
|
|
SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O
|
|
net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in
|
|
SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.568 -0.379
|
|
clock pessimism -0.192 -0.571
|
|
SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.638
|
|
arrival time 0.297
|
|
-------------------------------------------------------------------
|
|
slack 0.935
|
|
|
|
Slack (MET) : 0.944ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.815ns (logic 0.249ns (30.565%) route 0.566ns (69.435%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.378ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.400 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X127Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.569 -0.378
|
|
clock pessimism -0.192 -0.570
|
|
SLICE_X127Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]
|
|
-------------------------------------------------------------------
|
|
required time 0.735
|
|
arrival time 0.208
|
|
-------------------------------------------------------------------
|
|
slack 0.944
|
|
|
|
Slack (MET) : 0.944ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.815ns (logic 0.249ns (30.565%) route 0.566ns (69.435%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.378ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.400 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X127Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.569 -0.378
|
|
clock pessimism -0.192 -0.570
|
|
SLICE_X127Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]
|
|
-------------------------------------------------------------------
|
|
required time 0.735
|
|
arrival time 0.208
|
|
-------------------------------------------------------------------
|
|
slack 0.944
|
|
|
|
Slack (MET) : 0.947ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.819ns (logic 0.211ns (25.751%) route 0.608ns (74.249%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.377ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.164 -0.442 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q
|
|
net (fo=8, routed) 0.237 -0.205 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.047 -0.158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.371 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X125Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.570 -0.377
|
|
clock pessimism -0.192 -0.569
|
|
SLICE_X125Y65 FDCE (Remov_fdce_C_CLR) -0.165 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]
|
|
-------------------------------------------------------------------
|
|
required time 0.734
|
|
arrival time 0.213
|
|
-------------------------------------------------------------------
|
|
slack 0.947
|
|
|
|
Slack (MET) : 0.948ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.378ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.569 -0.378
|
|
clock pessimism -0.192 -0.570
|
|
SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]
|
|
-------------------------------------------------------------------
|
|
required time 0.735
|
|
arrival time 0.213
|
|
-------------------------------------------------------------------
|
|
slack 0.948
|
|
|
|
Slack (MET) : 0.948ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.378ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.569 -0.378
|
|
clock pessimism -0.192 -0.570
|
|
SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]
|
|
-------------------------------------------------------------------
|
|
required time 0.735
|
|
arrival time 0.213
|
|
-------------------------------------------------------------------
|
|
slack 0.948
|
|
|
|
Slack (MET) : 0.948ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.378ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.569 -0.378
|
|
clock pessimism -0.192 -0.570
|
|
SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]
|
|
-------------------------------------------------------------------
|
|
required time 0.735
|
|
arrival time 0.213
|
|
-------------------------------------------------------------------
|
|
slack 0.948
|
|
|
|
Slack (MET) : 0.948ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.378ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.569 -0.378
|
|
clock pessimism -0.192 -0.570
|
|
SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]
|
|
-------------------------------------------------------------------
|
|
required time 0.735
|
|
arrival time 0.213
|
|
-------------------------------------------------------------------
|
|
slack 0.948
|
|
|
|
Slack (MET) : 0.948ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.378ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.569 -0.378
|
|
clock pessimism -0.192 -0.570
|
|
SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]
|
|
-------------------------------------------------------------------
|
|
required time 0.735
|
|
arrival time 0.213
|
|
-------------------------------------------------------------------
|
|
slack 0.948
|
|
|
|
Slack (MET) : 0.952ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.822ns (logic 0.249ns (30.308%) route 0.573ns (69.692%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.035ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.379ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.407 0.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X125Y67 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.568 -0.379
|
|
clock pessimism -0.192 -0.571
|
|
SLICE_X125Y67 FDCE (Remov_fdce_C_CLR) -0.165 -0.736 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]
|
|
-------------------------------------------------------------------
|
|
required time 0.736
|
|
arrival time 0.215
|
|
-------------------------------------------------------------------
|
|
slack 0.952
|
|
|
|
Slack (MET) : 0.955ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.925ns (logic 0.246ns (26.589%) route 0.679ns (73.411%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.393 0.430 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X12Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X12Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.525
|
|
arrival time 0.430
|
|
-------------------------------------------------------------------
|
|
slack 0.955
|
|
|
|
Slack (MET) : 0.955ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.925ns (logic 0.246ns (26.589%) route 0.679ns (73.411%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.495ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.354 -0.495
|
|
SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=43, routed) 0.393 0.430 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X12Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism -0.196 -0.458
|
|
SLICE_X12Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.525
|
|
arrival time 0.430
|
|
-------------------------------------------------------------------
|
|
slack 0.955
|
|
|
|
Slack (MET) : 0.957ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.817ns (logic 0.249ns (30.489%) route 0.568ns (69.511%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.389ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.402 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X113Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
clock pessimism -0.192 -0.581
|
|
SLICE_X113Y75 FDCE (Remov_fdce_C_CLR) -0.165 -0.746 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 0.746
|
|
arrival time 0.210
|
|
-------------------------------------------------------------------
|
|
slack 0.957
|
|
|
|
Slack (MET) : 0.957ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.830ns (logic 0.249ns (29.992%) route 0.581ns (70.008%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.376ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.415 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X131Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.571 -0.376
|
|
clock pessimism -0.192 -0.568
|
|
SLICE_X131Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]
|
|
-------------------------------------------------------------------
|
|
required time 0.733
|
|
arrival time 0.224
|
|
-------------------------------------------------------------------
|
|
slack 0.957
|
|
|
|
Slack (MET) : 0.957ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.830ns (logic 0.249ns (29.992%) route 0.581ns (70.008%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.376ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.415 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X131Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.571 -0.376
|
|
clock pessimism -0.192 -0.568
|
|
SLICE_X131Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]
|
|
-------------------------------------------------------------------
|
|
required time 0.733
|
|
arrival time 0.224
|
|
-------------------------------------------------------------------
|
|
slack 0.957
|
|
|
|
Slack (MET) : 0.960ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.042ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.379ns
|
|
Source Clock Delay (SCD): -0.613ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0
|
|
SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O
|
|
net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in
|
|
SLICE_X113Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.568 -0.379
|
|
clock pessimism -0.192 -0.571
|
|
SLICE_X113Y65 FDCE (Remov_fdce_C_CLR) -0.092 -0.663 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.663
|
|
arrival time 0.297
|
|
-------------------------------------------------------------------
|
|
slack 0.960
|
|
|
|
Slack (MET) : 0.961ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.031ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.192 -0.575
|
|
SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time 0.221
|
|
-------------------------------------------------------------------
|
|
slack 0.961
|
|
|
|
Slack (MET) : 0.961ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.031ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.192 -0.575
|
|
SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time 0.221
|
|
-------------------------------------------------------------------
|
|
slack 0.961
|
|
|
|
Slack (MET) : 0.961ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.031ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.192 -0.575
|
|
SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time 0.221
|
|
-------------------------------------------------------------------
|
|
slack 0.961
|
|
|
|
Slack (MET) : 0.961ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.031ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.192 -0.575
|
|
SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time 0.221
|
|
-------------------------------------------------------------------
|
|
slack 0.961
|
|
|
|
Slack (MET) : 0.961ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.031ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.192 -0.575
|
|
SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time 0.221
|
|
-------------------------------------------------------------------
|
|
slack 0.961
|
|
|
|
Slack (MET) : 0.961ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[7]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.031ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.192 -0.575
|
|
SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time 0.221
|
|
-------------------------------------------------------------------
|
|
slack 0.961
|
|
|
|
Slack (MET) : 0.961ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[8]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.031ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.192 -0.575
|
|
SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time 0.221
|
|
-------------------------------------------------------------------
|
|
slack 0.961
|
|
|
|
Slack (MET) : 0.961ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[9]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.031ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.192 -0.575
|
|
SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 0.740
|
|
arrival time 0.221
|
|
-------------------------------------------------------------------
|
|
slack 0.961
|
|
|
|
Slack (MET) : 0.962ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[251]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.835ns (logic 0.249ns (29.836%) route 0.586ns (70.164%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.376ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.420 0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X130Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[251]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.571 -0.376
|
|
clock pessimism -0.192 -0.568
|
|
SLICE_X130Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[251]
|
|
-------------------------------------------------------------------
|
|
required time 0.733
|
|
arrival time 0.228
|
|
-------------------------------------------------------------------
|
|
slack 0.962
|
|
|
|
Slack (MET) : 0.962ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[254]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.835ns (logic 0.249ns (29.836%) route 0.586ns (70.164%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.376ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.420 0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X130Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[254]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.571 -0.376
|
|
clock pessimism -0.192 -0.568
|
|
SLICE_X130Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[254]
|
|
-------------------------------------------------------------------
|
|
required time 0.733
|
|
arrival time 0.228
|
|
-------------------------------------------------------------------
|
|
slack 0.962
|
|
|
|
Slack (MET) : 0.965ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[104]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.376ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[104]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.571 -0.376
|
|
clock pessimism -0.192 -0.568
|
|
SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[104]
|
|
-------------------------------------------------------------------
|
|
required time 0.708
|
|
arrival time 0.256
|
|
-------------------------------------------------------------------
|
|
slack 0.965
|
|
|
|
Slack (MET) : 0.965ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[105]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.376ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[105]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.571 -0.376
|
|
clock pessimism -0.192 -0.568
|
|
SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[105]
|
|
-------------------------------------------------------------------
|
|
required time 0.708
|
|
arrival time 0.256
|
|
-------------------------------------------------------------------
|
|
slack 0.965
|
|
|
|
Slack (MET) : 0.965ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[106]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.376ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[106]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.571 -0.376
|
|
clock pessimism -0.192 -0.568
|
|
SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[106]
|
|
-------------------------------------------------------------------
|
|
required time 0.708
|
|
arrival time 0.256
|
|
-------------------------------------------------------------------
|
|
slack 0.965
|
|
|
|
Slack (MET) : 0.965ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[107]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.376ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[107]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.571 -0.376
|
|
clock pessimism -0.192 -0.568
|
|
SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[107]
|
|
-------------------------------------------------------------------
|
|
required time 0.708
|
|
arrival time 0.256
|
|
-------------------------------------------------------------------
|
|
slack 0.965
|
|
|
|
Slack (MET) : 0.965ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[108]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.376ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[108]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.571 -0.376
|
|
clock pessimism -0.192 -0.568
|
|
SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[108]
|
|
-------------------------------------------------------------------
|
|
required time 0.708
|
|
arrival time 0.256
|
|
-------------------------------------------------------------------
|
|
slack 0.965
|
|
|
|
Slack (MET) : 0.965ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[109]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.376ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[109]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.571 -0.376
|
|
clock pessimism -0.192 -0.568
|
|
SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[109]
|
|
-------------------------------------------------------------------
|
|
required time 0.708
|
|
arrival time 0.256
|
|
-------------------------------------------------------------------
|
|
slack 0.965
|
|
|
|
Slack (MET) : 0.965ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[110]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.376ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[110]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.571 -0.376
|
|
clock pessimism -0.192 -0.568
|
|
SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[110]
|
|
-------------------------------------------------------------------
|
|
required time 0.708
|
|
arrival time 0.256
|
|
-------------------------------------------------------------------
|
|
slack 0.965
|
|
|
|
Slack (MET) : 0.965ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[111]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.376ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[111]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.571 -0.376
|
|
clock pessimism -0.192 -0.568
|
|
SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[111]
|
|
-------------------------------------------------------------------
|
|
required time 0.708
|
|
arrival time 0.256
|
|
-------------------------------------------------------------------
|
|
slack 0.965
|
|
|
|
Slack (MET) : 0.965ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.850ns (logic 0.211ns (24.816%) route 0.639ns (75.184%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.389ns
|
|
Source Clock Delay (SCD): -0.606ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.242 -0.606
|
|
SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.164 -0.442 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q
|
|
net (fo=8, routed) 0.237 -0.205 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.047 -0.158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 0.402 0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0
|
|
SLICE_X112Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
clock pessimism -0.192 -0.581
|
|
SLICE_X112Y75 FDCE (Remov_fdce_C_CLR) -0.140 -0.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.721
|
|
arrival time 0.244
|
|
-------------------------------------------------------------------
|
|
slack 0.965
|
|
|
|
Slack (MET) : 0.970ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.040ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1
|
|
SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.196 -0.457
|
|
SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.549
|
|
arrival time 0.421
|
|
-------------------------------------------------------------------
|
|
slack 0.970
|
|
|
|
Slack (MET) : 0.970ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.040ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1
|
|
SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.196 -0.457
|
|
SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.549
|
|
arrival time 0.421
|
|
-------------------------------------------------------------------
|
|
slack 0.970
|
|
|
|
Slack (MET) : 0.970ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.040ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.261ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1
|
|
SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.686 -0.261
|
|
clock pessimism -0.196 -0.457
|
|
SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.549
|
|
arrival time 0.421
|
|
-------------------------------------------------------------------
|
|
slack 0.970
|
|
|
|
Slack (MET) : 0.970ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR
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(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Path Group: **async_default**
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Path Type: Removal (Min at Fast Process Corner)
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Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
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Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%))
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Logic Levels: 1 (LUT1=1)
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Clock Path Skew: 0.040ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.261ns
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Source Clock Delay (SCD): -0.497ns
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Clock Pessimism Removal (CPR): 0.196ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock cpu_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.352 -0.497
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SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
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SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
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net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
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SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
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SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
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net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1
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SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR
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------------------------------------------------------------------- -------------------
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(clock cpu_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.686 -0.261
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clock pessimism -0.196 -0.457
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SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]
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-------------------------------------------------------------------
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required time 0.549
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arrival time 0.421
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-------------------------------------------------------------------
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slack 0.970
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