db9997b473
Pipelined multiplier: 3-stage LUT-based replaces shift_add, FSM simplified to 2-state
2026-06-25 22:09:20 +08:00
b3c0db19b9
Fix CRC32: use combinational stream_valid (was stuck-high causing repeated processing)
2026-06-25 20:53:56 +08:00
f8459f2478
Hardware CRC32 engine in matmul IP: 4-byte/cycle combinational, register at 0x010
2026-06-25 20:40:08 +08:00
956cd67773
Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines
2026-06-25 20:03:53 +08:00
57ba5d271d
Remove all debug and printf
2026-06-25 15:44:18 +08:00
4aba830a7d
Add for B1_C read channel
2026-06-25 04:04:18 +08:00
b5ec0d2926
Fix escaped quotes in display
2026-06-25 03:45:18 +08:00
9c6b321d59
Add in read channel to debug C register readback
2026-06-25 03:44:54 +08:00
3fb93131e5
Simplify ACCUM debug: show expression value only
2026-06-25 03:43:46 +08:00
86eab428a7
Use parenthesized pairwise addition to prevent synthesis truncation
2026-06-25 03:41:58 +08:00
fba86b01a8
Add in C_ACCUM to debug accumulation sum
2026-06-25 03:38:26 +08:00
4e409f870c
Register mult_p before accumulation to prevent synthesis glitches
2026-06-25 03:27:51 +08:00
d9d03b16c6
Fix: wait for ALL 4 multipliers to finish before accumulation
2026-06-25 03:07:49 +08:00
d3e1b5fda4
Add missing AXI4 ports: awlock/awcache/awprot/arlock/arcache/arprot
2026-06-25 00:53:28 +08:00
acb158a392
Update matmul RTL, remove shift_add_mult.v
2026-06-25 00:47:43 +08:00
641d055f18
User mods: matmul RTL + shift_add_mult + C program
2026-06-25 00:43:16 +08:00
f05c445ef3
Sync matmul IP (burst support) from no-fft
2026-06-25 00:12:02 +08:00
5972facc0a
Pipeline matmul multiplier: 2-stage to fix WNS
...
Split compute into stage1 (compute → partial) and
stage2 (partial → c_data). Halves CARRY4 chain depth
from 16 to ~8 levels. Compute cycles: 16 → 32.
2026-06-24 21:40:34 +08:00
ff6e572996
matmul_test: rewrite for ExtRAM flow, add IP error debug
...
- Rewrite main.c to read from ExtRAM (0x1c400000), compute
via matmul IP, write results back. Matches testbench
expectation of 10 groups.
- Add in matmul_axi_slave to trace error writes
2026-06-24 01:49:02 +08:00
fbc993b846
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
