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dd8d9c8f5f
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Add CDMA matmul sequencer
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2026-07-01 21:59:57 +08:00 |
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2080a700e9
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chore(sdk): update axi_ram.mif and mlkem_test.bin
Ultraworked with [Sisyphus](https://github.com/code-yeongyu/oh-my-openagent)
Co-authored-by: Sisyphus <clio-agent@sisyphuslabs.ai>
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2026-07-01 21:18:05 +08:00 |
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542495cb52
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fix: replace UNUSEDPARAM/UNUSEDSIGNAL with UNUSED for verilator lint
Verilator does not recognize UNUSEDPARAM or UNUSEDSIGNAL.
Correct suppression code is UNUSED.
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2026-06-30 02:10:07 +08:00 |
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81c636fb56
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perf(matmul): pre-fire DMA Ch0 load + inline wait/DMA start + XOR bank toggle
user-sample.c v2 optimizations:
- Pre-fire DMA Ch0 load at loop tail to overlap fully with IP compute
- Inline wait_matmul_done/wait_dma_done to eliminate function call overhead
- Inline DMA register writes, skip redundant STATUS_BUSY_BIT check
- Replace g%2 with XOR bank toggle (bank ^= 1)
- Cache volatile pointers in locals (ch0, ch1, mat_status, mat_ctrl)
Makefile: bump -O2 to -O3
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2026-06-26 03:39:32 +08:00 |
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f8459f2478
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Hardware CRC32 engine in matmul IP: 4-byte/cycle combinational, register at 0x010
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2026-06-25 20:40:08 +08:00 |
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956cd67773
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Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines
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2026-06-25 20:03:53 +08:00 |
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57ba5d271d
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Remove all debug and printf
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2026-06-25 15:44:18 +08:00 |
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a42568f635
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Clean production code: -O2, read CRC32 from ExtRAM, remove all debug
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2026-06-24 23:42:35 +08:00 |
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fbc993b846
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Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
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2026-06-23 01:22:45 +08:00 |
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