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f8459f2478
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Hardware CRC32 engine in matmul IP: 4-byte/cycle combinational, register at 0x010
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2026-06-25 20:40:08 +08:00 |
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956cd67773
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Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines
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2026-06-25 20:03:53 +08:00 |
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57ba5d271d
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Remove all debug and printf
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2026-06-25 15:44:18 +08:00 |
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a42568f635
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Clean production code: -O2, read CRC32 from ExtRAM, remove all debug
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2026-06-24 23:42:35 +08:00 |
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fbc993b846
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Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
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2026-06-23 01:22:45 +08:00 |
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