99c85f1a20
Rewrite burst logic with FFT-style state machine (W_IDLE/DATA/RESP, R_IDLE/DATA)
2026-06-25 00:22:30 +08:00
27d818390f
Remove assign s_axi_rlast (now procedural)
2026-06-25 00:18:09 +08:00
494b8b9c5b
Fix: s_axi_rlast must be output reg (assigned in always block)
2026-06-25 00:16:36 +08:00
20d5a541ad
Add burst write/read support to matmul AXI slave for DMA compatibility
2026-06-25 00:08:29 +08:00
d39b5ecdae
Revert pipeline: restore single-cycle compute
2026-06-24 22:23:53 +08:00
2edf058e97
Merge branch 'main' into no-fft
2026-06-24 21:41:50 +08:00
bbdc1fd7fe
Fix linter: remove placeholder, fix DVI reg declarations
2026-06-24 21:41:05 +08:00
5972facc0a
Pipeline matmul multiplier: 2-stage to fix WNS
...
Split compute into stage1 (compute → partial) and
stage2 (partial → c_data). Halves CARRY4 chain depth
from 16 to ~8 levels. Compute cycles: 16 → 32.
2026-06-24 21:40:34 +08:00
5ee2833a2b
Remove FFT module, tie off slave 6, fix linter issues
2026-06-24 20:54:33 +08:00
db2ad12dbb
Add verilator pragma to suppress BLKLOOPINIT in DelayBuffer.v
2026-06-24 20:41:52 +08:00
ff6e572996
matmul_test: rewrite for ExtRAM flow, add IP error debug
...
- Rewrite main.c to read from ExtRAM (0x1c400000), compute
via matmul IP, write results back. Matches testbench
expectation of 10 groups.
- Add in matmul_axi_slave to trace error writes
2026-06-24 01:49:02 +08:00
fe8eff0aa0
Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists
2026-06-23 01:33:56 +08:00
fbc993b846
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
