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956cd67773
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Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines
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2026-06-25 20:03:53 +08:00 |
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57ba5d271d
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Remove all debug and printf
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2026-06-25 15:44:18 +08:00 |
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54aa37adee
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Add debug output for C[0][0]/C[1][1]/C[2][3] of groups 0,1
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2026-06-25 03:03:10 +08:00 |
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9ecda4aa7a
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Fix CRC32 table, remove debug output
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2026-06-25 02:51:36 +08:00 |
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641d055f18
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User mods: matmul RTL + shift_add_mult + C program
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2026-06-25 00:43:16 +08:00 |
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4a67ca5c83
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Add debug output for group 0 write-back and group 1 compute
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2026-06-24 22:09:06 +08:00 |
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aaefb04737
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Sync asm/ (user-sample.c + Makefile) from test branch
MATMUL_GROUP_NUM defaults to 5000, overridable for fast local testing.
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2026-06-24 17:01:45 +08:00 |
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fbc993b846
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Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
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2026-06-23 01:22:45 +08:00 |
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