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fallensigh/ciciec2026
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69 Commits 5 Branches 1 Tag
956cd677735f92ead1089f95f3deb7e71c16e322
Commit Graph

6 Commits

Author SHA1 Message Date
FallenSigh
956cd67773 Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines 2026-06-25 20:03:53 +08:00
FallenSigh
6c77fa2e38 Remove FFT controller, tie off slave 6 2026-06-25 03:16:40 +08:00
FallenSigh
a2b3f72c76 Fix matmul AXI: add missing awlock/cache/prot ports, remove placeholder 2026-06-25 02:34:50 +08:00
FallenSigh
d5ad070ca0 Restore FFT module on main branch 2026-06-25 00:10:42 +08:00
FallenSigh
5ee2833a2b Remove FFT module, tie off slave 6, fix linter issues 2026-06-24 20:54:33 +08:00
FallenSigh
fbc993b846 Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC 2026-06-23 01:22:45 +08:00
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