7 Commits

Author	SHA1	Message	Date
FallenSigh	93d2fbd935	Optimize asm matmul dma software path	2026-07-06 00:13:01 +08:00
FallenSigh	a2b496ca8d	Restore timing + switch to polling + disable CPU interrupts (IE=0)	2026-06-26 01:01:48 +08:00
FallenSigh	956cd67773	Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines	2026-06-25 20:03:53 +08:00
FallenSigh	1660b283c4	Move DMA files to asm/, remove from common.mk	2026-06-24 23:52:30 +08:00
FallenSigh	5459538a04	Add dma.c to common.mk link list	2026-06-24 23:47:33 +08:00
FallenSigh	e35fa5884d	Use uncached ExtRAM access (0xBC400000) to bypass CPU data cache ... The open-la500 core has USE_CACHE enabled. Writes to 0x1c400000 go to the write-back data cache and never reach the SRAM model before the testbench checks ExtRAM. Use the 0xA0000000 uncached segment (same pattern as fft_dma/main.c).	2026-06-24 02:04:40 +08:00
FallenSigh	fbc993b846	Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC	2026-06-23 01:22:45 +08:00