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81c636fb56
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perf(matmul): pre-fire DMA Ch0 load + inline wait/DMA start + XOR bank toggle
user-sample.c v2 optimizations:
- Pre-fire DMA Ch0 load at loop tail to overlap fully with IP compute
- Inline wait_matmul_done/wait_dma_done to eliminate function call overhead
- Inline DMA register writes, skip redundant STATUS_BUSY_BIT check
- Replace g%2 with XOR bank toggle (bank ^= 1)
- Cache volatile pointers in locals (ch0, ch1, mat_status, mat_ctrl)
Makefile: bump -O2 to -O3
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2026-06-26 03:39:32 +08:00 |
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a2b496ca8d
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Restore timing + switch to polling + disable CPU interrupts (IE=0)
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2026-06-26 01:01:48 +08:00 |
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115466353d
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Remove timing instrumentation from user-sample.c
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2026-06-26 00:34:44 +08:00 |
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f8459f2478
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Hardware CRC32 engine in matmul IP: 4-byte/cycle combinational, register at 0x010
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2026-06-25 20:40:08 +08:00 |
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76b5f30c6b
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Move MATMUL_DONE to last line
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2026-06-25 20:11:45 +08:00 |
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d9483a9d39
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Add timing instrumentation for profiling (prologue/loop/epilogue/crc32)
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2026-06-25 20:10:31 +08:00 |
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956cd67773
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Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines
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2026-06-25 20:03:53 +08:00 |
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57ba5d271d
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Remove all debug and printf
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2026-06-25 15:44:18 +08:00 |
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54aa37adee
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Add debug output for C[0][0]/C[1][1]/C[2][3] of groups 0,1
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2026-06-25 03:03:10 +08:00 |
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9ecda4aa7a
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Fix CRC32 table, remove debug output
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2026-06-25 02:51:36 +08:00 |
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641d055f18
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User mods: matmul RTL + shift_add_mult + C program
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2026-06-25 00:43:16 +08:00 |
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4a67ca5c83
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Add debug output for group 0 write-back and group 1 compute
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2026-06-24 22:09:06 +08:00 |
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aaefb04737
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Sync asm/ (user-sample.c + Makefile) from test branch
MATMUL_GROUP_NUM defaults to 5000, overridable for fast local testing.
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2026-06-24 17:01:45 +08:00 |
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fbc993b846
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Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
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2026-06-23 01:22:45 +08:00 |
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