fallensigh/ciciec2026
Archived
0
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
109 Commits 5 Branches 1 Tag
7281df356fdb3b181e43b3643f048d9a82b87eb8
Commit Graph

53 Commits

Author SHA1 Message Date
FallenSigh
b8a4fcc30b Fix matmul_base address: 0x1f500000 -> 0xbf500000 
The open-la500 CPU maps 0xbfxx_xxxx to the peripheral address space
(crossbar sees 0x1fxx_xxxx). FFT uses 0xbf400000, CONFREG uses
0xbf20f100, UART uses 0xbf000000. Matmul must follow the same
convention.
 2026-06-24 01:58:29 +08:00
FallenSigh
ff6e572996 matmul_test: rewrite for ExtRAM flow, add IP error debug 
- Rewrite main.c to read from ExtRAM (0x1c400000), compute
  via matmul IP, write results back. Matches testbench
  expectation of 10 groups.
- Add  in matmul_axi_slave to trace error writes
 2026-06-24 01:49:02 +08:00
FallenSigh
fbc993b846 Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC 2026-06-23 01:22:45 +08:00