7281df356f
feat: optimize startup and linking
2026-07-05 17:27:26 +08:00
c37f493bcb
Compute matmul CRC before result store
2026-07-04 19:45:22 +08:00
b7553418fa
Add direct CDMA matmul path
2026-07-04 19:15:34 +08:00
a2b496ca8d
Restore timing + switch to polling + disable CPU interrupts (IE=0)
2026-06-26 01:01:48 +08:00
956cd67773
Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines
2026-06-25 20:03:53 +08:00
1660b283c4
Move DMA files to asm/, remove from common.mk
2026-06-24 23:52:30 +08:00
5459538a04
Add dma.c to common.mk link list
2026-06-24 23:47:33 +08:00
e35fa5884d
Use uncached ExtRAM access (0xBC400000) to bypass CPU data cache
...
The open-la500 core has USE_CACHE enabled. Writes to 0x1c400000
go to the write-back data cache and never reach the SRAM model
before the testbench checks ExtRAM. Use the 0xA0000000 uncached
segment (same pattern as fft_dma/main.c).
2026-06-24 02:04:40 +08:00
fbc993b846
Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC
2026-06-23 01:22:45 +08:00
