9 Commits

Author	SHA1	Message	Date
FallenSigh	fd03aaaaa1	Add matmul AXI master path	2026-07-01 23:13:28 +08:00
FallenSigh	09fc1aeb44	Add CDMA endpoint path for matmul transfers	2026-07-01 20:15:55 +08:00
FallenSigh	c5072d7170	feat: add ML-KEM accelerator with AXI slave wrapper ... Wrap mlkem_top in an AXI4 burst slave (mlkem_axi_slave) mapped to the freed FFT slot 6 at 0x1f400000 (virtual 0xbf400000). The core runs on sys_clk/2 (25 MHz); the wrapper handles the clock-domain crossing: start toggle->pulse, wait-stated byte-preload handshake, busy/done sync, and direct readback taps (ek/dk/ct/ss). CPU drives it via a register map (CTRL/STATUS/CONFIG, d/z/msg, preload + readback windows). Wire into soc_top on the existing axiOut_6 nets (no crossbar change), add mlkem_intr on intrpt[3]. Add sdk mlkem_test example running a KeyGen->Encaps->Decaps self-consistency round trip.	2026-06-30 01:39:35 +08:00
FallenSigh	956cd67773	Interrupt-driven wait: matmul HWI2 + DMA HWI1 direct CPU lines	2026-06-25 20:03:53 +08:00
FallenSigh	6c77fa2e38	Remove FFT controller, tie off slave 6	2026-06-25 03:16:40 +08:00
FallenSigh	a2b3f72c76	Fix matmul AXI: add missing awlock/cache/prot ports, remove placeholder	2026-06-25 02:34:50 +08:00
FallenSigh	d5ad070ca0	Restore FFT module on main branch	2026-06-25 00:10:42 +08:00
FallenSigh	5ee2833a2b	Remove FFT module, tie off slave 6, fix linter issues	2026-06-24 20:54:33 +08:00
FallenSigh	fbc993b846	Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC	2026-06-23 01:22:45 +08:00