FallenSigh d1b409f65f refactor(kg): bank_a -> sd_bram instance (1R+1W, real BRAM) ...

First of 3 banks promoted from async reg array to an sd_bram. Read port
muxed by phase (ST_M load drives pm_a_full, else dbg index); sd_bram's
internal rd_addr_r replaces the explicit pm_a_rd reg (identical 1-cyc
latency). Write port driven combinationally so the posedge write matches the
old nonblocking reg-array timing. 11/11 KAT PASS, byte-exact.

2026-06-28 21:26:35 +08:00

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