FallenSigh d1b409f65f refactor(kg): bank_a -> sd_bram instance (1R+1W, real BRAM) ...

First of 3 banks promoted from async reg array to an sd_bram. Read port
muxed by phase (ST_M load drives pm_a_full, else dbg index); sd_bram's
internal rd_addr_r replaces the explicit pm_a_rd reg (identical 1-cyc
latency). Write port driven combinationally so the posedge write matches the
old nonblocking reg-array timing. 11/11 KAT PASS, byte-exact.

2026-06-28 21:26:35 +08:00

..

common

feat: init mlkem project with Verilator test framework

2026-06-24 19:43:29 +08:00

comp_decomp

fix(tb): fix Vivado 2019.2 compilation and TB timing bugs

2026-06-25 21:32:19 +08:00

mod_add

fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh

2026-06-25 20:53:47 +08:00

ntt

fix(tb): fix Vivado 2019.2 compilation and TB timing bugs

2026-06-25 21:32:19 +08:00

poly_arith

fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh

2026-06-25 20:53:47 +08:00

poly_mul

fix(tb): fix Vivado 2019.2 compilation and TB timing bugs

2026-06-25 21:32:19 +08:00

rng

fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh

2026-06-25 20:53:47 +08:00

sample_cbd

feat(top): add shared keccak variants, arbiter, and mlkem_top integration

2026-06-26 03:35:37 +08:00

sample_ntt

fix(sample_ntt): suppress spurious 257th valid_o after last_o

2026-06-28 01:35:35 +08:00

sha3

refactor(kg): share a single keccak_core across G/H, SampleNTT, CBD (4->1)

2026-06-28 15:35:55 +08:00

storage

fix(tb): fix Vivado 2019.2 compilation and TB timing bugs

2026-06-25 21:32:19 +08:00

top

refactor(kg): bank_a -> sd_bram instance (1R+1W, real BRAM)

2026-06-28 21:26:35 +08:00