FallenSigh
4997657d7e
Adds 4 Verilator cases covering d_u=11 and d_v=5 (ML-KEM-1024), which the RTL already supports (d is 5-bit, products fit 24 bits). comp_decomp now 120/120 vectors. Also ignore .omo/ session runtime cache and archive the 06-27-sha3-g-test-specific-input trellis task. Verified all 10 modules pass both frameworks: - Verilator: 4334/4334 vectors - XSIM (Vivado 2019.2): all 11 testbenches green, separate committed vectors Oracles independently cross-checked vs hashlib (G/H/J/PRF) and FIPS 203 Alg 7/8/9/10/12 (sample_ntt, sample_cbd, ntt, poly_mul).
26 lines
578 B
JSON
26 lines
578 B
JSON
{
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"id": "sha3-g-test-specific-input",
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"name": "sha3-g-test-specific-input",
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"title": "修改sha3 TB测试G模式指定输入d=k=2",
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"description": "",
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"status": "in_progress",
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"dev_type": null,
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"scope": null,
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"package": null,
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"priority": "P2",
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"creator": "FallenSigh",
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"assignee": "FallenSigh",
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"createdAt": "2026-06-27",
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"completedAt": null,
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"branch": null,
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"base_branch": "main",
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"worktree_path": null,
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"commit": null,
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"pr_url": null,
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"subtasks": [],
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"children": [],
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"parent": null,
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"relatedFiles": [],
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"notes": "",
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"meta": {}
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} |