- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
7 lines
309 B
Makefile
7 lines
309 B
Makefile
tb_mod_add.o: ../sync_rtl/mod_add/TB/tb_mod_add.cpp Vmod_add_sync.h \
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/usr/share/verilator/include/verilated.h \
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/usr/share/verilator/include/verilated_config.h \
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/usr/share/verilator/include/verilatedos.h \
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/usr/share/verilator/include/verilated_types.h \
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/usr/share/verilator/include/verilated_funcs.h
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