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8fdf944555
- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
24 lines
731 B
C++
24 lines
731 B
C++
// Verilated -*- C++ -*-
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// DESCRIPTION: Verilator output: Design implementation internals
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// See Vmod_add_sync.h for the primary calling header
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#include "Vmod_add_sync__pch.h"
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void Vmod_add_sync___024root___ctor_var_reset(Vmod_add_sync___024root* vlSelf);
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Vmod_add_sync___024root::Vmod_add_sync___024root(Vmod_add_sync__Syms* symsp, const char* namep)
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{
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vlSymsp = symsp;
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vlNamep = strdup(namep);
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// Reset structure values
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Vmod_add_sync___024root___ctor_var_reset(this);
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}
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void Vmod_add_sync___024root::__Vconfigure(bool first) {
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(void)first; // Prevent unused variable warning
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}
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Vmod_add_sync___024root::~Vmod_add_sync___024root() {
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VL_DO_DANGLING(std::free(const_cast<char*>(vlNamep)), vlNamep);
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}
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