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- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
39 lines
1001 B
C++
39 lines
1001 B
C++
// Verilated -*- C++ -*-
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// DESCRIPTION: Verilator output: Symbol table internal header
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//
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// Internal details; most calling programs do not need this header,
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// unless using verilator public meta comments.
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#ifndef VERILATED_VMOD_ADD_SYNC__SYMS_H_
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#define VERILATED_VMOD_ADD_SYNC__SYMS_H_ // guard
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#include "verilated.h"
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// INCLUDE MODEL CLASS
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#include "Vmod_add_sync.h"
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// INCLUDE MODULE CLASSES
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#include "Vmod_add_sync___024root.h"
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// SYMS CLASS (contains all model state)
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class alignas(VL_CACHE_LINE_BYTES) Vmod_add_sync__Syms final : public VerilatedSyms {
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public:
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// INTERNAL STATE
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Vmod_add_sync* const __Vm_modelp;
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VlDeleter __Vm_deleter;
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bool __Vm_didInit = false;
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// MODULE INSTANCE STATE
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Vmod_add_sync___024root TOP;
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// CONSTRUCTORS
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Vmod_add_sync__Syms(VerilatedContext* contextp, const char* namep, Vmod_add_sync* modelp);
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~Vmod_add_sync__Syms();
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// METHODS
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const char* name() const { return TOP.vlNamep; }
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};
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#endif // guard
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