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- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
97 lines
3.6 KiB
C++
97 lines
3.6 KiB
C++
// Verilated -*- C++ -*-
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// DESCRIPTION: Verilator output: Primary model header
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//
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// This header should be included by all source files instantiating the design.
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// The class here is then constructed to instantiate the design.
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// See the Verilator manual for examples.
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#ifndef VERILATED_VMOD_ADD_SYNC_H_
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#define VERILATED_VMOD_ADD_SYNC_H_ // guard
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#include "verilated.h"
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class Vmod_add_sync__Syms;
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class Vmod_add_sync___024root;
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// This class is the main interface to the Verilated model
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class alignas(VL_CACHE_LINE_BYTES) Vmod_add_sync VL_NOT_FINAL : public VerilatedModel {
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private:
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// Symbol table holding complete model state (owned by this class)
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Vmod_add_sync__Syms* const vlSymsp;
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public:
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// CONSTEXPR CAPABILITIES
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// Verilated with --trace?
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static constexpr bool traceCapable = false;
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// PORTS
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// The application code writes and reads these signals to
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// propagate new values into/out from the Verilated model.
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VL_IN8(&clk,0,0);
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VL_IN8(&rst_n,0,0);
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VL_IN8(&valid_i,0,0);
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VL_OUT8(&ready_o,0,0);
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VL_OUT8(&valid_o,0,0);
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VL_IN8(&ready_i,0,0);
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VL_IN16(&a,11,0);
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VL_IN16(&b,11,0);
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VL_OUT16(&sum,11,0);
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// CELLS
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// Public to allow access to /* verilator public */ items.
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// Otherwise the application code can consider these internals.
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// Root instance pointer to allow access to model internals,
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// including inlined /* verilator public_flat_* */ items.
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Vmod_add_sync___024root* const rootp;
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// CONSTRUCTORS
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/// Construct the model; called by application code
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/// If contextp is null, then the model will use the default global context
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/// If name is "", then makes a wrapper with a
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/// single model invisible with respect to DPI scope names.
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explicit Vmod_add_sync(VerilatedContext* contextp, const char* name = "TOP");
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explicit Vmod_add_sync(const char* name = "TOP");
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/// Destroy the model; called (often implicitly) by application code
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virtual ~Vmod_add_sync();
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private:
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VL_UNCOPYABLE(Vmod_add_sync); ///< Copying not allowed
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public:
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// API METHODS
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/// Evaluate the model. Application must call when inputs change.
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void eval() { eval_step(); }
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/// Evaluate when calling multiple units/models per time step.
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void eval_step();
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/// Evaluate at end of a timestep for tracing, when using eval_step().
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/// Application must call after all eval() and before time changes.
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void eval_end_step() {}
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/// Simulation complete, run final blocks. Application must call on completion.
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void final();
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/// Are there scheduled events to handle?
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bool eventsPending();
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/// Returns time at next time slot. Aborts if !eventsPending()
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uint64_t nextTimeSlot();
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/// Trace signals in the model; called by application code
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void trace(VerilatedTraceBaseC* tfp, int levels, int options = 0) { contextp()->trace(tfp, levels, options); }
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/// Retrieve name of this model instance (as passed to constructor).
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const char* name() const;
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// Abstract methods from VerilatedModel
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const char* hierName() const override final;
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const char* modelName() const override final;
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unsigned threads() const override final;
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/// Prepare for cloning the model at the process level (e.g. fork in Linux)
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/// Release necessary resources. Called before cloning.
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void prepareClone() const;
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/// Re-init after cloning the model at the process level (e.g. fork in Linux)
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/// Re-allocate necessary resources. Called after cloning.
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void atClone() const;
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private:
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// Internal functions - trace registration
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void traceBaseModel(VerilatedTraceBaseC* tfp, int levels, int options);
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};
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#endif // guard
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