FallenSigh
92dafc9696
Add (* use_dsp = "no" *) to all modules containing multiplication operators to force LUT-based multiplication instead of DSP inference: - barrett_mul.v (3 multipliers x 7 instances = 21 ops) - comp_decomp_sync.v, sample_ntt_sync*.v, mlkem_top.v Also fix duplicate wire declaration of ct_bytes_rt in mlkem_top.v.
55 lines
1.5 KiB
Verilog
55 lines
1.5 KiB
Verilog
// barrett_mul.v - Barrett modular multiplication (a * b mod Q)
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//
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// Computes product = a * b mod Q using Barrett reduction.
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// Q = 3329, k = floor(2^24 / Q) = 5039
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//
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// Pure combinational, single-cycle latency.
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// All multiplication widths explicitly controlled to avoid Verilog truncation.
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(* use_dsp = "no" *)
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module barrett_mul (
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input [11:0] a,
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input [11:0] b,
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output [11:0] product
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);
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localparam Q = 3329;
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localparam K = 5039; // floor(2^24 / 3329)
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localparam R = 24;
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// Full product: a * b (both < 3329, product < 11,082,241 < 2^24)
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// Force 24-bit evaluation by extending operand
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wire [23:0] p;
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assign p = {12'd0, a} * b;
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// Extend p to 37 bits for multiplication with K
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wire [36:0] p_ext;
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assign p_ext = {13'd0, p};
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// Compute t_shifted = (p * K) >> 24
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// Use explicit wire for the product to control width
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/* verilator lint_off UNUSEDSIGNAL */
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wire [36:0] t_product;
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/* verilator lint_on UNUSEDSIGNAL */
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assign t_product = p_ext * K;
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wire [12:0] t_shifted;
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assign t_shifted = t_product[36:R];
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// q_approx = t_shifted * Q
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wire [24:0] q_approx;
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assign q_approx = t_shifted * Q;
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// r = p - q_approx
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wire [24:0] r0;
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assign r0 = {1'b0, p} - q_approx;
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// Conditional subtract Q (at most twice)
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wire [24:0] r1;
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assign r1 = (r0 >= Q) ? (r0 - Q) : r0;
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wire [11:0] r2;
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assign r2 = (r1[11:0] >= Q) ? (r1[11:0] - Q) : r1[11:0];
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assign product = (r1 >= Q) ? r2 : r1[11:0];
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endmodule
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