mlkem-sync

fallensigh/mlkem-sync

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Commit Graph

Author	SHA1	Message	Date
FallenSigh	717a9929b6	fix(rtl,scripts): replace combinational divider with Barrett multiplication, add synthesis include_dirs, set 50MHz clock - Replace / and % operators in comp_decomp_sync with Barrett multiply-by-reciprocal (dividend * 5039 >> 24) + correction step. Eliminates ~100 CARRY4 divider chain. - Add include_dirs for sources_1 fileset so Windows Vivado synthesis finds defines.vh. - Change CLK_PERIOD from 10.0 (100MHz) to 40.0 (50MHz) to reflect actual target.	2026-06-30 00:23:43 +08:00
FallenSigh	92dafc9696	fix(rtl): add use_dsp="no" attributes, fix duplicate wire declaration Add (* use_dsp = "no" ) to all modules containing multiplication operators to force LUT-based multiplication instead of DSP inference: - barrett_mul.v (3 multipliers x 7 instances = 21 ops) - comp_decomp_sync.v, sample_ntt_sync.v, mlkem_top.v Also fix duplicate wire declaration of ct_bytes_rt in mlkem_top.v.	2026-06-29 23:23:58 +08:00
FallenSigh	a369a421b7	feat(phase3): implement storage BRAMs and Compress/Decompress Phase 3.1 + 3.3: - sd_bram.v: simple dual-port RAM (behavioral, auto-infer to BRAM) - s_bram.v: single-port RAM (rd_en/wr_en, write priority) - comp_decomp_sync.v: streaming compress/decompress with round-half-up Verified: storage 5/5, comp_decomp 60/60 all PASS	2026-06-24 23:28:06 +08:00

Author

SHA1

Message

Date

FallenSigh

717a9929b6

fix(rtl,scripts): replace combinational divider with Barrett multiplication, add synthesis include_dirs, set 50MHz clock

- Replace / and % operators in comp_decomp_sync with Barrett multiply-by-reciprocal
  (dividend * 5039 >> 24) + correction step. Eliminates ~100 CARRY4 divider chain.
- Add include_dirs for sources_1 fileset so Windows Vivado synthesis finds defines.vh.
- Change CLK_PERIOD from 10.0 (100MHz) to 40.0 (50MHz) to reflect actual target.

2026-06-30 00:23:43 +08:00

FallenSigh

92dafc9696

fix(rtl): add use_dsp="no" attributes, fix duplicate wire declaration

Add (* use_dsp = "no" *) to all modules containing multiplication
operators to force LUT-based multiplication instead of DSP inference:
- barrett_mul.v (3 multipliers x 7 instances = 21 ops)
- comp_decomp_sync.v, sample_ntt_sync*.v, mlkem_top.v

Also fix duplicate wire declaration of ct_bytes_rt in mlkem_top.v.

2026-06-29 23:23:58 +08:00

FallenSigh

a369a421b7

feat(phase3): implement storage BRAMs and Compress/Decompress

Phase 3.1 + 3.3:
- sd_bram.v: simple dual-port RAM (behavioral, auto-infer to BRAM)
- s_bram.v: single-port RAM (rd_en/wr_en, write priority)
- comp_decomp_sync.v: streaming compress/decompress with round-half-up

Verified: storage 5/5, comp_decomp 60/60 all PASS

2026-06-24 23:28:06 +08:00

3 Commits