fix(rtl): add use_dsp="no" attributes, fix duplicate wire declaration

Add (* use_dsp = "no" *) to all modules containing multiplication
operators to force LUT-based multiplication instead of DSP inference:
- barrett_mul.v (3 multipliers x 7 instances = 21 ops)
- comp_decomp_sync.v, sample_ntt_sync*.v, mlkem_top.v

Also fix duplicate wire declaration of ct_bytes_rt in mlkem_top.v.

sync_rtl/ntt/barrett_mul.v

@@ -6,6 +6,7 @@
 // Pure combinational, single-cycle latency.
 // All multiplication widths explicitly controlled to avoid Verilog truncation.
 
+(* use_dsp = "no" *)
 module barrett_mul (
     input  [11:0] a,
     input  [11:0] b,