From 92dafc9696a5afc1de15a05c9e7721b5340d4350 Mon Sep 17 00:00:00 2001
From: FallenSigh <fallensigh@gmail.com>
Date: Mon, 29 Jun 2026 23:23:58 +0800
Subject: [PATCH] fix(rtl): add use_dsp="no" attributes, fix duplicate wire
 declaration

Add (* use_dsp = "no" *) to all modules containing multiplication
operators to force LUT-based multiplication instead of DSP inference:
- barrett_mul.v (3 multipliers x 7 instances = 21 ops)
- comp_decomp_sync.v, sample_ntt_sync*.v, mlkem_top.v

Also fix duplicate wire declaration of ct_bytes_rt in mlkem_top.v.
---
 sync_rtl/comp_decomp/comp_decomp_sync.v      | 1 +
 sync_rtl/ntt/barrett_mul.v                   | 1 +
 sync_rtl/sample_ntt/sample_ntt_sync.v        | 1 +
 sync_rtl/sample_ntt/sample_ntt_sync_shared.v | 1 +
 sync_rtl/top/mlkem_top.v                     | 2 +-
 5 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/sync_rtl/comp_decomp/comp_decomp_sync.v b/sync_rtl/comp_decomp/comp_decomp_sync.v
index 2c199da..65c0056 100644
--- a/sync_rtl/comp_decomp/comp_decomp_sync.v
+++ b/sync_rtl/comp_decomp/comp_decomp_sync.v
@@ -10,6 +10,7 @@
 
 `include "sync_rtl/common/defines.vh"
 
+(* use_dsp = "no" *)
 module comp_decomp_sync (
     input         clk,
     input         rst_n,
diff --git a/sync_rtl/ntt/barrett_mul.v b/sync_rtl/ntt/barrett_mul.v
index 2bf7745..6d5249a 100644
--- a/sync_rtl/ntt/barrett_mul.v
+++ b/sync_rtl/ntt/barrett_mul.v
@@ -6,6 +6,7 @@
 // Pure combinational, single-cycle latency.
 // All multiplication widths explicitly controlled to avoid Verilog truncation.
 
+(* use_dsp = "no" *)
 module barrett_mul (
     input  [11:0] a,
     input  [11:0] b,
diff --git a/sync_rtl/sample_ntt/sample_ntt_sync.v b/sync_rtl/sample_ntt/sample_ntt_sync.v
index 3a20aee..62539fe 100644
--- a/sync_rtl/sample_ntt/sample_ntt_sync.v
+++ b/sync_rtl/sample_ntt/sample_ntt_sync.v
@@ -31,6 +31,7 @@
 `include "sync_rtl/common/defines.vh"
 
 /* verilator lint_off UNUSEDPARAM */
+(* use_dsp = "no" *)
 module sample_ntt_sync #(parameter K = 4) (
 /* verilator lint_on UNUSEDPARAM */
     input              clk,
diff --git a/sync_rtl/sample_ntt/sample_ntt_sync_shared.v b/sync_rtl/sample_ntt/sample_ntt_sync_shared.v
index da03515..9896ba2 100644
--- a/sync_rtl/sample_ntt/sample_ntt_sync_shared.v
+++ b/sync_rtl/sample_ntt/sample_ntt_sync_shared.v
@@ -44,6 +44,7 @@
 `include "sync_rtl/common/defines.vh"
 
 /* verilator lint_off UNUSEDPARAM */
+(* use_dsp = "no" *)
 module sample_ntt_sync_shared #(parameter K = 4) (
 /* verilator lint_on UNUSEDPARAM */
     input              clk,
diff --git a/sync_rtl/top/mlkem_top.v b/sync_rtl/top/mlkem_top.v
index 1a73615..d803baa 100644
--- a/sync_rtl/top/mlkem_top.v
+++ b/sync_rtl/top/mlkem_top.v
@@ -22,6 +22,7 @@
 
 `include "sync_rtl/common/defines.vh"
 
+(* use_dsp = "no" *)
 module mlkem_top #(
     parameter KMAX = 4               // storage sizing (worst case = ML-KEM-1024)
 ) (
@@ -133,7 +134,6 @@ module mlkem_top #(
     wire [11:0] c1_bytes_rt = 12'd32 * {7'b0, du_rt} * {9'b0, k_r};  // 640/960/1408
     wire [11:0] c2_bytes_rt = 12'd32 * {7'b0, dv_rt};                 // 128/128/160
     wire [11:0] ct_bytes_rt = c1_bytes_rt + c2_bytes_rt;             // 768/1088/1568
-    wire [11:0] ct_bytes_rt = c1_bytes_rt + c2_bytes_rt;             // 768/1088/1568
     // Shared secret out: Encaps drives ss_r = K directly. Decaps implicit reject:
     // ss = (c' == c) ? K' : K-bar. K' is in ss_r, K-bar in kbar_r; dec_reject is
     // the latched c' != c flag from D7 (0 for KeyGen/Encaps, so ss_r passes through).