feat: init mlkem project with Verilator test framework

- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready)
- sync_rtl/mod_add/: modular adder example with Verilator C++ TB
- test_framework/: Python-driven Verilator compile/sim/compare pipeline
- test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS
- .trellis/spec/: RTL and test_framework conventions documented

obj_dir/Vmod_add_sync__Syms__Slow.cpp

@@ -0,0 +1,28 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Symbol table implementation internals
+
+#include "Vmod_add_sync__pch.h"
+
+Vmod_add_sync__Syms::Vmod_add_sync__Syms(VerilatedContext* contextp, const char* namep, Vmod_add_sync* modelp)
+    : VerilatedSyms{contextp}
+    // Setup internal state of the Syms class
+    , __Vm_modelp{modelp}
+    // Setup top module instance
+    , TOP{this, namep}
+{
+    // Check resources
+    Verilated::stackCheck(250);
+    // Setup sub module instances
+    // Configure time unit / time precision
+    _vm_contextp__->timeunit(-12);
+    _vm_contextp__->timeprecision(-12);
+    // Setup each module's pointers to their submodules
+    // Setup each module's pointer back to symbol table (for public functions)
+    TOP.__Vconfigure(true);
+    // Setup scopes
+}
+
+Vmod_add_sync__Syms::~Vmod_add_sync__Syms() {
+    // Tear down scopes
+    // Tear down sub module instances
+}