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- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
29 lines
906 B
C++
29 lines
906 B
C++
// Verilated -*- C++ -*-
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// DESCRIPTION: Verilator output: Symbol table implementation internals
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#include "Vmod_add_sync__pch.h"
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Vmod_add_sync__Syms::Vmod_add_sync__Syms(VerilatedContext* contextp, const char* namep, Vmod_add_sync* modelp)
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: VerilatedSyms{contextp}
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// Setup internal state of the Syms class
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, __Vm_modelp{modelp}
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// Setup top module instance
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, TOP{this, namep}
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{
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// Check resources
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Verilated::stackCheck(250);
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// Setup sub module instances
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// Configure time unit / time precision
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_vm_contextp__->timeunit(-12);
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_vm_contextp__->timeprecision(-12);
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// Setup each module's pointers to their submodules
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// Setup each module's pointer back to symbol table (for public functions)
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TOP.__Vconfigure(true);
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// Setup scopes
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}
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Vmod_add_sync__Syms::~Vmod_add_sync__Syms() {
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// Tear down scopes
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// Tear down sub module instances
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}
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