feat: init mlkem project with Verilator test framework

- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready)
- sync_rtl/mod_add/: modular adder example with Verilator C++ TB
- test_framework/: Python-driven Verilator compile/sim/compare pipeline
- test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS
- .trellis/spec/: RTL and test_framework conventions documented
This commit is contained in:
2026-06-24 19:43:29 +08:00
commit 8fdf944555
216 changed files with 24140 additions and 0 deletions

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obj_dir/Vmod_add_sync.cpp Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Model implementation (design independent parts)
#include "Vmod_add_sync__pch.h"
//============================================================
// Constructors
Vmod_add_sync::Vmod_add_sync(VerilatedContext* _vcontextp__, const char* _vcname__)
: VerilatedModel{*_vcontextp__}
, vlSymsp{new Vmod_add_sync__Syms(contextp(), _vcname__, this)}
, clk{vlSymsp->TOP.clk}
, rst_n{vlSymsp->TOP.rst_n}
, valid_i{vlSymsp->TOP.valid_i}
, ready_o{vlSymsp->TOP.ready_o}
, valid_o{vlSymsp->TOP.valid_o}
, ready_i{vlSymsp->TOP.ready_i}
, a{vlSymsp->TOP.a}
, b{vlSymsp->TOP.b}
, sum{vlSymsp->TOP.sum}
, rootp{&(vlSymsp->TOP)}
{
// Register model with the context
contextp()->addModel(this);
}
Vmod_add_sync::Vmod_add_sync(const char* _vcname__)
: Vmod_add_sync(Verilated::threadContextp(), _vcname__)
{
}
//============================================================
// Destructor
Vmod_add_sync::~Vmod_add_sync() {
delete vlSymsp;
}
//============================================================
// Evaluation function
#ifdef VL_DEBUG
void Vmod_add_sync___024root___eval_debug_assertions(Vmod_add_sync___024root* vlSelf);
#endif // VL_DEBUG
void Vmod_add_sync___024root___eval_static(Vmod_add_sync___024root* vlSelf);
void Vmod_add_sync___024root___eval_initial(Vmod_add_sync___024root* vlSelf);
void Vmod_add_sync___024root___eval_settle(Vmod_add_sync___024root* vlSelf);
void Vmod_add_sync___024root___eval(Vmod_add_sync___024root* vlSelf);
void Vmod_add_sync::eval_step() {
VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vmod_add_sync::eval_step\n"); );
#ifdef VL_DEBUG
// Debug assertions
Vmod_add_sync___024root___eval_debug_assertions(&(vlSymsp->TOP));
#endif // VL_DEBUG
vlSymsp->__Vm_deleter.deleteAll();
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Initial\n"););
Vmod_add_sync___024root___eval_static(&(vlSymsp->TOP));
Vmod_add_sync___024root___eval_initial(&(vlSymsp->TOP));
Vmod_add_sync___024root___eval_settle(&(vlSymsp->TOP));
vlSymsp->__Vm_didInit = true;
}
VL_DEBUG_IF(VL_DBG_MSGF("+ Eval\n"););
Vmod_add_sync___024root___eval(&(vlSymsp->TOP));
// Evaluate cleanup
Verilated::endOfEval(vlSymsp->__Vm_evalMsgQp);
}
//============================================================
// Events and timing
bool Vmod_add_sync::eventsPending() { return false; }
uint64_t Vmod_add_sync::nextTimeSlot() {
VL_FATAL_MT(__FILE__, __LINE__, "", "No delays in the design");
return 0;
}
//============================================================
// Utilities
const char* Vmod_add_sync::name() const {
return vlSymsp->name();
}
//============================================================
// Invoke final blocks
void Vmod_add_sync___024root___eval_final(Vmod_add_sync___024root* vlSelf);
VL_ATTR_COLD void Vmod_add_sync::final() {
Vmod_add_sync___024root___eval_final(&(vlSymsp->TOP));
}
//============================================================
// Implementations of abstract methods from VerilatedModel
const char* Vmod_add_sync::hierName() const { return vlSymsp->name(); }
const char* Vmod_add_sync::modelName() const { return "Vmod_add_sync"; }
unsigned Vmod_add_sync::threads() const { return 1; }
void Vmod_add_sync::prepareClone() const { contextp()->prepareClone(); }
void Vmod_add_sync::atClone() const {
contextp()->threadPoolpOnClone();
}