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- sync_rtl/common/: skid_buffer, pipeline_reg, defines (valid/ready) - sync_rtl/mod_add/: modular adder example with Verilator C++ TB - test_framework/: Python-driven Verilator compile/sim/compare pipeline - test_framework/modules/mod_add/: 50-vector test plan, full鏈路 PASS - .trellis/spec/: RTL and test_framework conventions documented
105 lines
3.4 KiB
C++
105 lines
3.4 KiB
C++
// Verilated -*- C++ -*-
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// DESCRIPTION: Verilator output: Model implementation (design independent parts)
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#include "Vmod_add_sync__pch.h"
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//============================================================
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// Constructors
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Vmod_add_sync::Vmod_add_sync(VerilatedContext* _vcontextp__, const char* _vcname__)
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: VerilatedModel{*_vcontextp__}
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, vlSymsp{new Vmod_add_sync__Syms(contextp(), _vcname__, this)}
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, clk{vlSymsp->TOP.clk}
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, rst_n{vlSymsp->TOP.rst_n}
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, valid_i{vlSymsp->TOP.valid_i}
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, ready_o{vlSymsp->TOP.ready_o}
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, valid_o{vlSymsp->TOP.valid_o}
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, ready_i{vlSymsp->TOP.ready_i}
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, a{vlSymsp->TOP.a}
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, b{vlSymsp->TOP.b}
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, sum{vlSymsp->TOP.sum}
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, rootp{&(vlSymsp->TOP)}
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{
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// Register model with the context
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contextp()->addModel(this);
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}
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Vmod_add_sync::Vmod_add_sync(const char* _vcname__)
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: Vmod_add_sync(Verilated::threadContextp(), _vcname__)
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{
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}
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//============================================================
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// Destructor
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Vmod_add_sync::~Vmod_add_sync() {
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delete vlSymsp;
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}
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//============================================================
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// Evaluation function
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#ifdef VL_DEBUG
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void Vmod_add_sync___024root___eval_debug_assertions(Vmod_add_sync___024root* vlSelf);
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#endif // VL_DEBUG
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void Vmod_add_sync___024root___eval_static(Vmod_add_sync___024root* vlSelf);
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void Vmod_add_sync___024root___eval_initial(Vmod_add_sync___024root* vlSelf);
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void Vmod_add_sync___024root___eval_settle(Vmod_add_sync___024root* vlSelf);
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void Vmod_add_sync___024root___eval(Vmod_add_sync___024root* vlSelf);
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void Vmod_add_sync::eval_step() {
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VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vmod_add_sync::eval_step\n"); );
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#ifdef VL_DEBUG
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// Debug assertions
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Vmod_add_sync___024root___eval_debug_assertions(&(vlSymsp->TOP));
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#endif // VL_DEBUG
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vlSymsp->__Vm_deleter.deleteAll();
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if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) {
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VL_DEBUG_IF(VL_DBG_MSGF("+ Initial\n"););
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Vmod_add_sync___024root___eval_static(&(vlSymsp->TOP));
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Vmod_add_sync___024root___eval_initial(&(vlSymsp->TOP));
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Vmod_add_sync___024root___eval_settle(&(vlSymsp->TOP));
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vlSymsp->__Vm_didInit = true;
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}
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VL_DEBUG_IF(VL_DBG_MSGF("+ Eval\n"););
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Vmod_add_sync___024root___eval(&(vlSymsp->TOP));
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// Evaluate cleanup
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Verilated::endOfEval(vlSymsp->__Vm_evalMsgQp);
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}
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//============================================================
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// Events and timing
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bool Vmod_add_sync::eventsPending() { return false; }
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uint64_t Vmod_add_sync::nextTimeSlot() {
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VL_FATAL_MT(__FILE__, __LINE__, "", "No delays in the design");
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return 0;
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}
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//============================================================
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// Utilities
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const char* Vmod_add_sync::name() const {
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return vlSymsp->name();
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}
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//============================================================
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// Invoke final blocks
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void Vmod_add_sync___024root___eval_final(Vmod_add_sync___024root* vlSelf);
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VL_ATTR_COLD void Vmod_add_sync::final() {
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Vmod_add_sync___024root___eval_final(&(vlSymsp->TOP));
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}
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//============================================================
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// Implementations of abstract methods from VerilatedModel
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const char* Vmod_add_sync::hierName() const { return vlSymsp->name(); }
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const char* Vmod_add_sync::modelName() const { return "Vmod_add_sync"; }
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unsigned Vmod_add_sync::threads() const { return 1; }
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void Vmod_add_sync::prepareClone() const { contextp()->prepareClone(); }
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void Vmod_add_sync::atClone() const {
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contextp()->threadPoolpOnClone();
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}
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