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chore(task): archive 06-25-vivado-verilog-tb

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FallenSigh
2026-06-25 20:59:32 +08:00
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.trellis/tasks/archive/2026-06/06-25-vivado-verilog-tb/implement.jsonl Normal file
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{"file": ".trellis/spec/rtl/verilator-conventions.md", "reason": "RTL conventions: clock period 10ns, valid/ready timing protocol, pipeline_reg behavior"}