FallenSigh 171ffd91d3 chore(task): archive 06-25-vivado-verilog-tb

2026-06-25 20:59:32 +08:00

.claude

feat: init mlkem project with Verilator test framework

2026-06-24 19:43:29 +08:00

.opencode

feat: init mlkem project with Verilator test framework

2026-06-24 19:43:29 +08:00

.trellis

chore(task): archive 06-25-vivado-verilog-tb

2026-06-25 20:59:32 +08:00

sync_rtl

fix(tb): fix Vivado 2019.2 compatibility and add run_tb.sh

2026-06-25 20:53:47 +08:00

test_framework

feat(sha3_chain): add simple SHA3_G integration test

2026-06-25 00:22:08 +08:00

.gitignore

chore: add .gitignore, remove build artifacts from tracking

2026-06-24 19:43:40 +08:00

AGENTS.md

feat: init mlkem project with Verilator test framework

2026-06-24 19:43:29 +08:00

run_tb.sh

fix(tb): fix run_tb.sh TCL variable extraction

2026-06-25 20:57:30 +08:00

Description

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52 MiB

Languages

Verilog 81.2%

Python 9.9%

Tcl 5.1%

Shell 3.8%