1110 lines
37 KiB
Verilog
1110 lines
37 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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//1f00_0000 apb
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//1f10_0000 dvi
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//1f20_0000 confreg
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//1f30_0000 dma
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`include "config.h"
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module soc_top #(parameter SIMULATION=1'b0)
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(
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input clk,
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input reset,
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//图像输出信号
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output [2:0] video_red, //红色像素，3位
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output [2:0] video_green, //绿色像素，3位
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output [1:0] video_blue, //蓝色像素，2位
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output video_hsync, //行同步（水平同步）信号
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output video_vsync, //场同步（垂直同步）信号
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output video_clk, //像素时钟输出
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output video_de, //行数据有效信号，用于区分消隐区
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input [3:0] touch_btn, //BTN1~BTN4，按钮开关，按下时为1
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input [31:0] dip_sw, //32位拨码开关，拨到“ON”时为1
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output [15:0] leds, //16位LED，输出时1点亮
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output [7:0] dpy0, //数码管低位信号，包括小数点，输出1点亮
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output [7:0] dpy1, //数码管高位信号，包括小数点，输出1点亮
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//BaseRAM信号
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inout [31:0] base_ram_data, //BaseRAM数据，低8位与CPLD串口控制器共享
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output [19:0] base_ram_addr, //BaseRAM地址
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output [ 3:0] base_ram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0
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output base_ram_ce_n, //BaseRAM片选，低有效
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output base_ram_oe_n, //BaseRAM读使能，低有效
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output base_ram_we_n, //BaseRAM写使能，低有效
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//ExtRAM信号
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inout [31:0] ext_ram_data, //ExtRAM数据
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output [19:0] ext_ram_addr, //ExtRAM地址
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output [ 3:0] ext_ram_be_n, //ExtRAM字节使能，低有效。如果不使用字节使能，请保持为0
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output ext_ram_ce_n, //ExtRAM片选，低有效
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output ext_ram_oe_n, //ExtRAM读使能，低有效
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output ext_ram_we_n, //ExtRAM写使能，低有效
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//------uart-------
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inout UART_RX, //串口RX接收
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inout UART_TX //串口TX发送
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);
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wire cpu_clk;
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wire cpu_resetn;
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wire sys_clk;
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wire sys_resetn;
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wire pll_locked;
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generate if(SIMULATION) begin: sim_clk
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//simulation clk.
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reg clk_sim;
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initial begin
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clk_sim = 1'b0;
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end
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always #15 clk_sim = ~clk_sim;
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assign cpu_clk = clk_sim;
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assign sys_clk = clk;
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rst_sync u_rst_sys(
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.clk(sys_clk),
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.rst_n_in(~reset),
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.rst_n_out(sys_resetn)
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);
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rst_sync u_rst_cpu(
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.clk(cpu_clk),
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.rst_n_in(sys_resetn),
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.rst_n_out(cpu_resetn)
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);
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end
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else begin: pll_clk
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clk_pll u_clk_pll(
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.cpu_clk (cpu_clk),
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.sys_clk (sys_clk),
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.resetn (~reset),
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.locked (pll_locked),
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.clk_in1 (clk)
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);
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rst_sync u_rst_sys(
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.clk(sys_clk),
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.rst_n_in(pll_locked),
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.rst_n_out(sys_resetn)
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);
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rst_sync u_rst_cpu(
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.clk(cpu_clk),
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.rst_n_in(sys_resetn),
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.rst_n_out(cpu_resetn)
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);
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end
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endgenerate
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//debug signals
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wire [31:0] debug_wb_pc;
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wire [31:0] debug_wb_inst;
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wire [3 :0] debug_wb_rf_wen;
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wire [4 :0] debug_wb_rf_wnum;
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wire [31:0] debug_wb_rf_wdata;
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//cpu axi
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wire [3 :0] cpu_arid ;
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wire [31:0] cpu_araddr ;
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wire [7 :0] cpu_arlen ;
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wire [2 :0] cpu_arsize ;
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wire [1 :0] cpu_arburst;
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wire [1 :0] cpu_arlock ;
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wire [3 :0] cpu_arcache;
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wire [2 :0] cpu_arprot ;
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wire cpu_arvalid;
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wire cpu_arready;
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wire [3 :0] cpu_rid ;
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wire [31:0] cpu_rdata ;
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wire [1 :0] cpu_rresp ;
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wire cpu_rlast ;
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wire cpu_rvalid ;
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wire cpu_rready ;
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wire [3 :0] cpu_awid ;
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wire [31:0] cpu_awaddr ;
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wire [7 :0] cpu_awlen ;
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wire [2 :0] cpu_awsize ;
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wire [1 :0] cpu_awburst;
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wire [1 :0] cpu_awlock ;
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wire [3 :0] cpu_awcache;
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wire [2 :0] cpu_awprot ;
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wire cpu_awvalid;
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wire cpu_awready;
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wire [3 :0] cpu_wid ;
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wire [31:0] cpu_wdata ;
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wire [3 :0] cpu_wstrb ;
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wire cpu_wlast ;
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wire cpu_wvalid ;
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wire cpu_wready ;
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wire [3 :0] cpu_bid ;
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wire [1 :0] cpu_bresp ;
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wire cpu_bvalid ;
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wire cpu_bready ;
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wire cpu_sync_awid_4 ;
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wire cpu_bid_4 ;
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wire cpu_sync_arid_4 ;
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wire cpu_rid_4 ;
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//cpu axi sync
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wire [3 :0] cpu_sync_arid ;
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wire [31:0] cpu_sync_araddr ;
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wire [7 :0] cpu_sync_arlen ;
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wire [2 :0] cpu_sync_arsize ;
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wire [1 :0] cpu_sync_arburst;
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wire cpu_sync_arlock ;
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wire [3 :0] cpu_sync_arcache;
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wire [2 :0] cpu_sync_arprot ;
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wire cpu_sync_arvalid;
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wire cpu_sync_arready;
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wire [3 :0] cpu_sync_rid ;
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wire [31:0] cpu_sync_rdata ;
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wire [1 :0] cpu_sync_rresp ;
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wire cpu_sync_rlast ;
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wire cpu_sync_rvalid ;
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wire cpu_sync_rready ;
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wire [3 :0] cpu_sync_awid ;
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wire [31:0] cpu_sync_awaddr ;
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wire [7 :0] cpu_sync_awlen ;
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wire [2 :0] cpu_sync_awsize ;
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wire [1 :0] cpu_sync_awburst;
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wire cpu_sync_awlock ;
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wire [3 :0] cpu_sync_awcache;
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wire [2 :0] cpu_sync_awprot ;
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wire cpu_sync_awvalid;
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wire cpu_sync_awready;
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wire [3 :0] cpu_sync_wid ;
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wire [31:0] cpu_sync_wdata ;
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wire [3 :0] cpu_sync_wstrb ;
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wire cpu_sync_wlast ;
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wire cpu_sync_wvalid ;
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wire cpu_sync_wready ;
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wire [3 :0] cpu_sync_bid ;
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wire [1 :0] cpu_sync_bresp ;
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wire cpu_sync_bvalid ;
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wire cpu_sync_bready ;
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//axi ram
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wire [4 :0] ram_arid ;
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wire [31:0] ram_araddr ;
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wire [7 :0] ram_arlen ;
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wire [2 :0] ram_arsize ;
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wire [1 :0] ram_arburst;
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wire ram_arlock ;
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wire [3 :0] ram_arcache;
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wire [2 :0] ram_arprot ;
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wire ram_arvalid;
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wire ram_arready;
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wire [4 :0] ram_rid ;
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wire [31:0] ram_rdata ;
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wire [1 :0] ram_rresp ;
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wire ram_rlast ;
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wire ram_rvalid ;
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wire ram_rready ;
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wire [4 :0] ram_awid ;
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wire [31:0] ram_awaddr ;
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wire [7 :0] ram_awlen ;
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wire [2 :0] ram_awsize ;
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wire [1 :0] ram_awburst;
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wire ram_awlock ;
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wire [3 :0] ram_awcache;
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wire [2 :0] ram_awprot ;
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wire ram_awvalid;
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wire ram_awready;
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wire [4 :0] ram_wid ;
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wire [31:0] ram_wdata ;
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wire [3 :0] ram_wstrb ;
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wire ram_wlast ;
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wire ram_wvalid ;
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wire ram_wready ;
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wire [4 :0] ram_bid ;
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wire [1 :0] ram_bresp ;
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wire ram_bvalid ;
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wire ram_bready ;
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//uart axi
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wire uart_arready;
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wire [ 4:0] uart_rid;
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wire [31:0] uart_rdata;
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wire [ 1:0] uart_rresp;
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wire uart_rlast;
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wire uart_rvalid;
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wire uart_awready;
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wire uart_wready;
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wire [ 4:0] uart_bid;
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wire [ 1:0] uart_bresp;
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wire uart_bvalid;
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wire [ 4:0] uart_arid;
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wire [31:0] uart_araddr;
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wire [ 7:0] uart_arlen;
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wire [ 2:0] uart_arsize;
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wire [ 1:0] uart_arburst;
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wire uart_arlock;
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wire [ 3:0] uart_arcache;
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wire [ 2:0] uart_arprot;
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wire uart_arvalid;
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wire uart_rready;
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wire [ 4:0] uart_awid;
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wire [31:0] uart_awaddr;
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wire [ 7:0] uart_awlen;
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wire [ 2:0] uart_awsize;
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wire [ 1:0] uart_awburst;
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wire uart_awlock;
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wire [ 3:0] uart_awcache;
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wire [ 2:0] uart_awprot;
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wire uart_awvalid;
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wire [ 4:0] uart_wid;
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wire [31:0] uart_wdata;
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wire [ 3:0] uart_wstrb;
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wire uart_wlast;
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wire uart_wvalid;
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wire uart_bready;
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wire irq_rx;
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//uart
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wire UART_CTS, UART_RTS;
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wire UART_DTR, UART_DSR;
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wire UART_RI, UART_DCD;
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assign UART_CTS = 1'b0;
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assign UART_DSR = 1'b0;
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assign UART_DCD = 1'b0;
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assign UART_RI = 1'b0;
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wire uart0_int ;
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wire uart0_txd_o ;
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wire uart0_txd_i ;
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wire uart0_txd_oe;
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wire uart0_rxd_o ;
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wire uart0_rxd_i ;
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wire uart0_rxd_oe;
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wire uart0_rts_o ;
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wire uart0_cts_i ;
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wire uart0_dsr_i ;
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wire uart0_dcd_i ;
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wire uart0_dtr_o ;
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wire uart0_ri_i ;
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assign UART_RX = uart0_rxd_oe ? 1'bz : uart0_rxd_o ;
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assign UART_TX = uart0_txd_oe ? 1'bz : uart0_txd_o ;
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assign UART_RTS = uart0_rts_o ;
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assign UART_DTR = uart0_dtr_o ;
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assign uart0_txd_i = UART_TX;
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assign uart0_rxd_i = UART_RX;
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assign uart0_cts_i = UART_CTS;
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assign uart0_dcd_i = UART_DCD;
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assign uart0_dsr_i = UART_DSR;
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assign uart0_ri_i = UART_RI ;
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//dma master axi
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wire [3 :0] dma_m_arid ;
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wire [31:0] dma_m_araddr ;
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wire [7 :0] dma_m_arlen ;
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wire [2 :0] dma_m_arsize ;
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wire [1 :0] dma_m_arburst;
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wire dma_m_arlock ;
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wire [3 :0] dma_m_arcache;
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wire [2 :0] dma_m_arprot ;
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wire dma_m_arvalid;
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wire dma_m_arready;
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wire [3 :0] dma_m_rid ;
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wire [31:0] dma_m_rdata ;
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wire [1 :0] dma_m_rresp ;
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wire dma_m_rlast ;
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wire dma_m_rvalid ;
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wire dma_m_rready ;
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wire [3 :0] dma_m_awid ;
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wire [31:0] dma_m_awaddr ;
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wire [7 :0] dma_m_awlen ;
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wire [2 :0] dma_m_awsize ;
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wire [1 :0] dma_m_awburst;
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wire dma_m_awlock ;
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wire [3 :0] dma_m_awcache;
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wire [2 :0] dma_m_awprot ;
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wire dma_m_awvalid;
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wire dma_m_awready;
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wire [3 :0] dma_m_wid ;
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wire [31:0] dma_m_wdata ;
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wire [3 :0] dma_m_wstrb ;
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wire dma_m_wlast ;
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wire dma_m_wvalid ;
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wire dma_m_wready ;
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wire [3 :0] dma_m_bid ;
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wire [1 :0] dma_m_bresp ;
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wire dma_m_bvalid ;
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wire dma_m_bready ;
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assign dma_m_arid = 4'b0 ;
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assign dma_m_araddr = 32'h0;
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assign dma_m_arlen = 8'b0 ;
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assign dma_m_arsize = 3'b0 ;
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assign dma_m_arburst = 2'b0;
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assign dma_m_arlock = 1'b0;
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assign dma_m_arcache = 4'b0;
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assign dma_m_arprot = 3'b0;
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assign dma_m_arvalid = 1'b0;
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assign dma_m_rready = 1'b1;
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assign dma_m_awid = 4'b0;
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assign dma_m_awaddr = 32'b0;
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assign dma_m_awlen = 8'b0;
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assign dma_m_awsize = 3'b0;
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assign dma_m_awburst = 2'b0;
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assign dma_m_awlock = 1'b0;
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assign dma_m_awcache = 4'b0;
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assign dma_m_awprot = 3'b0;
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assign dma_m_awvalid = 1'b1;
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assign dma_m_wid = 4'b0;
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assign dma_m_wdata = 32'b0;
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assign dma_m_wstrb = 4'b0;
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assign dma_m_wlast = 1'b0;
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assign dma_m_wvalid = 1'b0;
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assign dma_m_bready = 1'b1;
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wire [4 :0] dma_s_arid ;
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wire [31:0] dma_s_araddr ;
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wire [7 :0] dma_s_arlen ;
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wire [2 :0] dma_s_arsize ;
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wire [1 :0] dma_s_arburst;
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wire dma_s_arlock ;
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wire [3 :0] dma_s_arcache;
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wire [2 :0] dma_s_arprot ;
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wire dma_s_arvalid;
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wire dma_s_arready;
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wire [4 :0] dma_s_rid ;
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wire [31:0] dma_s_rdata ;
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wire [1 :0] dma_s_rresp ;
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wire dma_s_rlast ;
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wire dma_s_rvalid ;
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wire dma_s_rready ;
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wire [4 :0] dma_s_awid ;
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wire [31:0] dma_s_awaddr ;
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wire [7 :0] dma_s_awlen ;
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wire [2 :0] dma_s_awsize ;
|
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wire [1 :0] dma_s_awburst;
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wire dma_s_awlock ;
|
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wire [3 :0] dma_s_awcache;
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wire [2 :0] dma_s_awprot ;
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wire dma_s_awvalid;
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wire dma_s_awready;
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wire [31:0] dma_s_wdata ;
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wire [3 :0] dma_s_wstrb ;
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wire dma_s_wlast ;
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wire dma_s_wvalid ;
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wire dma_s_wready ;
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wire [4 :0] dma_s_bid ;
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wire [1 :0] dma_s_bresp ;
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wire dma_s_bvalid ;
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wire dma_s_bready ;
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wire dma_finish ;
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assign dma_s_arready = 1'b1;
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assign dma_s_rid = 5'b0;
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assign dma_s_rdata = 32'b0;
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assign dma_s_rresp = 2'b0;
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assign dma_s_rlast = 1'b0;
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assign dma_s_rvalid = 1'b0;
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assign dma_s_awready = 1'b1;
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assign dma_s_wready = 1'b1;
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assign dma_s_bid = 5'b0;
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assign dma_s_bresp = 2'b0;
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assign dma_s_bvalid = 1'b0;
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// reserved
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||
wire [4 :0] axiOut_1_arid ;
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||
wire [31:0] axiOut_1_araddr ;
|
||
wire [7 :0] axiOut_1_arlen ;
|
||
wire [2 :0] axiOut_1_arsize ;
|
||
wire [1 :0] axiOut_1_arburst;
|
||
wire axiOut_1_arlock ;
|
||
wire [3 :0] axiOut_1_arcache;
|
||
wire [2 :0] axiOut_1_arprot ;
|
||
wire axiOut_1_arvalid;
|
||
wire axiOut_1_arready;
|
||
wire [4 :0] axiOut_1_rid ;
|
||
wire [31:0] axiOut_1_rdata ;
|
||
wire [1 :0] axiOut_1_rresp ;
|
||
wire axiOut_1_rlast ;
|
||
wire axiOut_1_rvalid ;
|
||
wire axiOut_1_rready ;
|
||
wire [4 :0] axiOut_1_awid ;
|
||
wire [31:0] axiOut_1_awaddr ;
|
||
wire [7 :0] axiOut_1_awlen ;
|
||
wire [2 :0] axiOut_1_awsize ;
|
||
wire [1 :0] axiOut_1_awburst;
|
||
wire axiOut_1_awlock ;
|
||
wire [3 :0] axiOut_1_awcache;
|
||
wire [2 :0] axiOut_1_awprot ;
|
||
wire axiOut_1_awvalid;
|
||
wire axiOut_1_awready;
|
||
wire [4 :0] axiOut_1_wid ;
|
||
wire [31:0] axiOut_1_wdata ;
|
||
wire [3 :0] axiOut_1_wstrb ;
|
||
wire axiOut_1_wlast ;
|
||
wire axiOut_1_wvalid ;
|
||
wire axiOut_1_wready ;
|
||
wire [4 :0] axiOut_1_bid ;
|
||
wire [1 :0] axiOut_1_bresp ;
|
||
wire axiOut_1_bvalid ;
|
||
wire axiOut_1_bready ;
|
||
|
||
assign axiOut_1_arready = 1'b1;
|
||
assign axiOut_1_rid = 5'b0;
|
||
assign axiOut_1_rdata = 32'b0;
|
||
assign axiOut_1_rresp = 2'b0;
|
||
assign axiOut_1_rlast = 1'b0;
|
||
assign axiOut_1_rvalid = 1'b0;
|
||
assign axiOut_1_awready = 1'b1;
|
||
assign axiOut_1_wready = 1'b1;
|
||
assign axiOut_1_bid = 5'b0;
|
||
assign axiOut_1_bresp = 2'b0;
|
||
assign axiOut_1_bvalid = 1'b0;
|
||
|
||
|
||
//axi dvi
|
||
wire [4 :0] dvi_arid ;
|
||
wire [31:0] dvi_araddr ;
|
||
wire [7 :0] dvi_arlen ;
|
||
wire [2 :0] dvi_arsize ;
|
||
wire [1 :0] dvi_arburst;
|
||
wire [1 :0] dvi_arlock ;
|
||
wire [3 :0] dvi_arcache;
|
||
wire [2 :0] dvi_arprot ;
|
||
wire dvi_arvalid;
|
||
wire dvi_arready;
|
||
wire [4 :0] dvi_rid ;
|
||
wire [31:0] dvi_rdata ;
|
||
wire [1 :0] dvi_rresp ;
|
||
wire dvi_rlast ;
|
||
wire dvi_rvalid ;
|
||
wire dvi_rready ;
|
||
wire [4 :0] dvi_awid ;
|
||
wire [31:0] dvi_awaddr ;
|
||
wire [7 :0] dvi_awlen ;
|
||
wire [2 :0] dvi_awsize ;
|
||
wire [1 :0] dvi_awburst;
|
||
wire [1 :0] dvi_awlock ;
|
||
wire [3 :0] dvi_awcache;
|
||
wire [2 :0] dvi_awprot ;
|
||
wire dvi_awvalid;
|
||
wire dvi_awready;
|
||
wire [4 :0] dvi_wid ;
|
||
wire [31:0] dvi_wdata ;
|
||
wire [3 :0] dvi_wstrb ;
|
||
wire dvi_wlast ;
|
||
wire dvi_wvalid ;
|
||
wire dvi_wready ;
|
||
wire [4 :0] dvi_bid ;
|
||
wire [1 :0] dvi_bresp ;
|
||
wire dvi_bvalid ;
|
||
wire dvi_bready ;
|
||
|
||
assign dvi_arready = 1'b1;
|
||
assign dvi_rid = 5'b0;
|
||
assign dvi_rdata = 32'b0;
|
||
assign dvi_rresp = 2'b0;
|
||
assign dvi_rlast = 1'b0;
|
||
assign dvi_rvalid = 1'b0;
|
||
assign dvi_awready = 1'b1;
|
||
assign dvi_wready = 1'b1;
|
||
assign dvi_bid = 5'b0;
|
||
assign dvi_bresp = 2'b0;
|
||
assign dvi_bvalid = 1'b0;
|
||
|
||
//axi confreg
|
||
wire [4 :0] confreg_arid ;
|
||
wire [31:0] confreg_araddr ;
|
||
wire [7 :0] confreg_arlen ;
|
||
wire [2 :0] confreg_arsize ;
|
||
wire [1 :0] confreg_arburst;
|
||
wire confreg_arlock ;
|
||
wire [3 :0] confreg_arcache;
|
||
wire [2 :0] confreg_arprot ;
|
||
wire confreg_arvalid;
|
||
wire confreg_arready;
|
||
wire [4 :0] confreg_rid ;
|
||
wire [31:0] confreg_rdata ;
|
||
wire [1 :0] confreg_rresp ;
|
||
wire confreg_rlast ;
|
||
wire confreg_rvalid ;
|
||
wire confreg_rready ;
|
||
wire [4 :0] confreg_awid ;
|
||
wire [31:0] confreg_awaddr ;
|
||
wire [7 :0] confreg_awlen ;
|
||
wire [2 :0] confreg_awsize ;
|
||
wire [1 :0] confreg_awburst;
|
||
wire confreg_awlock ;
|
||
wire [3 :0] confreg_awcache;
|
||
wire [2 :0] confreg_awprot ;
|
||
wire confreg_awvalid;
|
||
wire confreg_awready;
|
||
wire [4 :0] confreg_wid ;
|
||
wire [31:0] confreg_wdata ;
|
||
wire [3 :0] confreg_wstrb ;
|
||
wire confreg_wlast ;
|
||
wire confreg_wvalid ;
|
||
wire confreg_wready ;
|
||
wire [4 :0] confreg_bid ;
|
||
wire [1 :0] confreg_bresp ;
|
||
wire confreg_bvalid ;
|
||
wire confreg_bready ;
|
||
|
||
//slave 6 FFT/IFFT
|
||
wire [4 :0] fft_arid ;
|
||
wire [31:0] fft_araddr ;
|
||
wire [7 :0] fft_arlen ;
|
||
wire [2 :0] fft_arsize ;
|
||
wire [1 :0] fft_arburst;
|
||
wire fft_arlock ;
|
||
wire [3 :0] fft_arcache;
|
||
wire [2 :0] fft_arprot ;
|
||
wire fft_arvalid;
|
||
wire fft_arready;
|
||
wire [4 :0] fft_rid ;
|
||
wire [31:0] fft_rdata ;
|
||
wire [1 :0] fft_rresp ;
|
||
wire fft_rlast ;
|
||
wire fft_rvalid ;
|
||
wire fft_rready ;
|
||
wire [4 :0] fft_awid ;
|
||
wire [31:0] fft_awaddr ;
|
||
wire [7 :0] fft_awlen ;
|
||
wire [2 :0] fft_awsize ;
|
||
wire [1 :0] fft_awburst;
|
||
wire fft_awlock ;
|
||
wire [3 :0] fft_awcache;
|
||
wire [2 :0] fft_awprot ;
|
||
wire fft_awvalid;
|
||
wire fft_awready;
|
||
wire [4 :0] fft_wid ;
|
||
wire [31:0] fft_wdata ;
|
||
wire [3 :0] fft_wstrb ;
|
||
wire fft_wlast ;
|
||
wire fft_wvalid ;
|
||
wire fft_wready ;
|
||
wire [4 :0] fft_bid ;
|
||
wire [1 :0] fft_bresp ;
|
||
wire fft_bvalid ;
|
||
wire fft_bready ;
|
||
wire fft_finish ;
|
||
|
||
assign fft_arready = 1'b1;
|
||
assign fft_rid = 5'b0;
|
||
assign fft_rdata = 32'b0;
|
||
assign fft_rresp = 2'b0;
|
||
assign fft_rlast = 1'b0;
|
||
assign fft_rvalid = 1'b0;
|
||
assign fft_awready = 1'b1;
|
||
assign fft_wready = 1'b1;
|
||
assign fft_bid = 5'b0;
|
||
assign fft_bresp = 2'b0;
|
||
assign fft_bvalid = 1'b0;
|
||
|
||
//slave 7
|
||
wire [4 :0] axiOut_7_arid ;
|
||
wire [31:0] axiOut_7_araddr ;
|
||
wire [7 :0] axiOut_7_arlen ;
|
||
wire [2 :0] axiOut_7_arsize ;
|
||
wire [1 :0] axiOut_7_arburst;
|
||
wire axiOut_7_arlock ;
|
||
wire [3 :0] axiOut_7_arcache;
|
||
wire [2 :0] axiOut_7_arprot ;
|
||
wire axiOut_7_arvalid;
|
||
wire axiOut_7_arready;
|
||
wire [4 :0] axiOut_7_rid ;
|
||
wire [31:0] axiOut_7_rdata ;
|
||
wire [1 :0] axiOut_7_rresp ;
|
||
wire axiOut_7_rlast ;
|
||
wire axiOut_7_rvalid ;
|
||
wire axiOut_7_rready ;
|
||
wire [4 :0] axiOut_7_awid ;
|
||
wire [31:0] axiOut_7_awaddr ;
|
||
wire [7 :0] axiOut_7_awlen ;
|
||
wire [2 :0] axiOut_7_awsize ;
|
||
wire [1 :0] axiOut_7_awburst;
|
||
wire axiOut_7_awlock ;
|
||
wire [3 :0] axiOut_7_awcache;
|
||
wire [2 :0] axiOut_7_awprot ;
|
||
wire axiOut_7_awvalid;
|
||
wire axiOut_7_awready;
|
||
wire [4 :0] axiOut_7_wid ;
|
||
wire [31:0] axiOut_7_wdata ;
|
||
wire [3 :0] axiOut_7_wstrb ;
|
||
wire axiOut_7_wlast ;
|
||
wire axiOut_7_wvalid ;
|
||
wire axiOut_7_wready ;
|
||
wire [4 :0] axiOut_7_bid ;
|
||
wire [1 :0] axiOut_7_bresp ;
|
||
wire axiOut_7_bvalid ;
|
||
wire axiOut_7_bready ;
|
||
|
||
assign axiOut_7_arready = 1'b1;
|
||
assign axiOut_7_rid = 5'b0;
|
||
assign axiOut_7_rdata = 32'b0;
|
||
assign axiOut_7_rresp = 2'b0;
|
||
assign axiOut_7_rlast = 1'b0;
|
||
assign axiOut_7_rvalid = 1'b0;
|
||
assign axiOut_7_awready = 1'b1;
|
||
assign axiOut_7_wready = 1'b1;
|
||
assign axiOut_7_bid = 5'b0;
|
||
assign axiOut_7_bresp = 2'b0;
|
||
assign axiOut_7_bvalid = 1'b0;
|
||
|
||
wire confreg_int;
|
||
|
||
AxiCrossbar_2x8 u_AxiCrossbar_2x8 (
|
||
.clk ( sys_clk ),
|
||
.resetn ( sys_resetn ),
|
||
|
||
//master 0
|
||
//aw
|
||
.axiIn_0_awvalid ( cpu_sync_awvalid ),
|
||
.axiIn_0_awready ( cpu_sync_awready ),
|
||
.axiIn_0_awaddr ( cpu_sync_awaddr ),
|
||
.axiIn_0_awid ( cpu_sync_awid ),
|
||
.axiIn_0_awlen ( cpu_sync_awlen ),
|
||
.axiIn_0_awsize ( cpu_sync_awsize ),
|
||
.axiIn_0_awburst ( cpu_sync_awburst ),
|
||
.axiIn_0_awlock ( cpu_sync_awlock ),
|
||
.axiIn_0_awcache ( cpu_sync_awcache ),
|
||
.axiIn_0_awprot ( cpu_sync_awprot ),
|
||
//w
|
||
.axiIn_0_wvalid ( cpu_sync_wvalid ),
|
||
.axiIn_0_wready ( cpu_sync_wready ),
|
||
.axiIn_0_wdata ( cpu_sync_wdata ),
|
||
.axiIn_0_wstrb ( cpu_sync_wstrb ),
|
||
.axiIn_0_wlast ( cpu_sync_wlast ),
|
||
//b
|
||
.axiIn_0_bready ( cpu_sync_bready ),
|
||
.axiIn_0_bvalid ( cpu_sync_bvalid ),
|
||
.axiIn_0_bid ( cpu_sync_bid ),
|
||
.axiIn_0_bresp ( cpu_sync_bresp ),
|
||
//ar
|
||
.axiIn_0_arvalid ( cpu_sync_arvalid ),
|
||
.axiIn_0_arready ( cpu_sync_arready ),
|
||
.axiIn_0_araddr ( cpu_sync_araddr ),
|
||
.axiIn_0_arid ( cpu_sync_arid ),
|
||
.axiIn_0_arlen ( cpu_sync_arlen ),
|
||
.axiIn_0_arsize ( cpu_sync_arsize ),
|
||
.axiIn_0_arburst ( cpu_sync_arburst ),
|
||
.axiIn_0_arlock ( cpu_sync_arlock ),
|
||
.axiIn_0_arcache ( cpu_sync_arcache ),
|
||
.axiIn_0_arprot ( cpu_sync_arprot ),
|
||
//r
|
||
.axiIn_0_rvalid ( cpu_sync_rvalid ),
|
||
.axiIn_0_rready ( cpu_sync_rready ),
|
||
.axiIn_0_rdata ( cpu_sync_rdata ),
|
||
.axiIn_0_rid ( cpu_sync_rid ),
|
||
.axiIn_0_rresp ( cpu_sync_rresp ),
|
||
.axiIn_0_rlast ( cpu_sync_rlast ),
|
||
|
||
//master 1
|
||
//aw
|
||
.axiIn_1_awvalid ( dma_m_awvalid ),
|
||
.axiIn_1_awready ( dma_m_awready ),
|
||
.axiIn_1_awaddr ( dma_m_awaddr ),
|
||
.axiIn_1_awid ( dma_m_awid ),
|
||
.axiIn_1_awlen ( dma_m_awlen ),
|
||
.axiIn_1_awsize ( dma_m_awsize ),
|
||
.axiIn_1_awburst ( dma_m_awburst ),
|
||
.axiIn_1_awlock ( dma_m_awlock ),
|
||
.axiIn_1_awcache ( dma_m_awcache ),
|
||
.axiIn_1_awprot ( dma_m_awprot ),
|
||
//w
|
||
.axiIn_1_wvalid ( dma_m_wvalid ),
|
||
.axiIn_1_wready ( dma_m_wready ),
|
||
.axiIn_1_wdata ( dma_m_wdata ),
|
||
.axiIn_1_wstrb ( dma_m_wstrb ),
|
||
.axiIn_1_wlast ( dma_m_wlast ),
|
||
//b
|
||
.axiIn_1_bready ( dma_m_bready ),
|
||
.axiIn_1_bvalid ( dma_m_bvalid ),
|
||
.axiIn_1_bid ( dma_m_bid ),
|
||
.axiIn_1_bresp ( dma_m_bresp ),
|
||
//ar
|
||
.axiIn_1_arvalid ( dma_m_arvalid ),
|
||
.axiIn_1_arready ( dma_m_arready ),
|
||
.axiIn_1_araddr ( dma_m_araddr ),
|
||
.axiIn_1_arid ( dma_m_arid ),
|
||
.axiIn_1_arlen ( dma_m_arlen ),
|
||
.axiIn_1_arsize ( dma_m_arsize ),
|
||
.axiIn_1_arburst ( dma_m_arburst ),
|
||
.axiIn_1_arlock ( dma_m_arlock ),
|
||
.axiIn_1_arcache ( dma_m_arcache ),
|
||
.axiIn_1_arprot ( dma_m_arprot ),
|
||
//r
|
||
.axiIn_1_rvalid ( dma_m_rvalid ),
|
||
.axiIn_1_rready ( dma_m_rready ),
|
||
.axiIn_1_rdata ( dma_m_rdata ),
|
||
.axiIn_1_rid ( dma_m_rid ),
|
||
.axiIn_1_rresp ( dma_m_rresp ),
|
||
.axiIn_1_rlast ( dma_m_rlast ),
|
||
|
||
//slave 0
|
||
//aw
|
||
.axiOut_0_awvalid ( ram_awvalid ),
|
||
.axiOut_0_awready ( ram_awready ),
|
||
.axiOut_0_awaddr ( ram_awaddr ),
|
||
.axiOut_0_awid ( ram_awid ),
|
||
.axiOut_0_awlen ( ram_awlen ),
|
||
.axiOut_0_awsize ( ram_awsize ),
|
||
.axiOut_0_awburst ( ram_awburst ),
|
||
.axiOut_0_awlock ( ram_awlock ),
|
||
.axiOut_0_awcache ( ram_awcache ),
|
||
.axiOut_0_awprot ( ram_awprot ),
|
||
//w
|
||
.axiOut_0_wvalid ( ram_wvalid ),
|
||
.axiOut_0_wready ( ram_wready ),
|
||
.axiOut_0_wdata ( ram_wdata ),
|
||
.axiOut_0_wstrb ( ram_wstrb ),
|
||
.axiOut_0_wlast ( ram_wlast ),
|
||
//b
|
||
.axiOut_0_bready ( ram_bready ),
|
||
.axiOut_0_bvalid ( ram_bvalid ),
|
||
.axiOut_0_bid ( ram_bid ),
|
||
.axiOut_0_bresp ( ram_bresp ),
|
||
//ar
|
||
.axiOut_0_arvalid ( ram_arvalid ),
|
||
.axiOut_0_arready ( ram_arready ),
|
||
.axiOut_0_araddr ( ram_araddr ),
|
||
.axiOut_0_arid ( ram_arid ),
|
||
.axiOut_0_arlen ( ram_arlen ),
|
||
.axiOut_0_arsize ( ram_arsize ),
|
||
.axiOut_0_arburst ( ram_arburst ),
|
||
.axiOut_0_arlock ( ram_arlock ),
|
||
.axiOut_0_arcache ( ram_arcache ),
|
||
.axiOut_0_arprot ( ram_arprot ),
|
||
//r
|
||
.axiOut_0_rvalid ( ram_rvalid ),
|
||
.axiOut_0_rready ( ram_rready ),
|
||
.axiOut_0_rdata ( ram_rdata ),
|
||
.axiOut_0_rid ( ram_rid ),
|
||
.axiOut_0_rresp ( ram_rresp ),
|
||
.axiOut_0_rlast ( ram_rlast ),
|
||
|
||
//slave 1
|
||
//aw
|
||
.axiOut_1_awvalid ( axiOut_1_awvalid ),
|
||
.axiOut_1_awready ( axiOut_1_awready ),
|
||
.axiOut_1_awaddr ( axiOut_1_awaddr ),
|
||
.axiOut_1_awid ( axiOut_1_awid ),
|
||
.axiOut_1_awlen ( axiOut_1_awlen ),
|
||
.axiOut_1_awsize ( axiOut_1_awsize ),
|
||
.axiOut_1_awburst ( axiOut_1_awburst ),
|
||
.axiOut_1_awlock ( axiOut_1_awlock ),
|
||
.axiOut_1_awcache ( axiOut_1_awcache ),
|
||
.axiOut_1_awprot ( axiOut_1_awprot ),
|
||
//w
|
||
.axiOut_1_wvalid ( axiOut_1_wvalid ),
|
||
.axiOut_1_wready ( axiOut_1_wready ),
|
||
.axiOut_1_wdata ( axiOut_1_wdata ),
|
||
.axiOut_1_wstrb ( axiOut_1_wstrb ),
|
||
.axiOut_1_wlast ( axiOut_1_wlast ),
|
||
//b
|
||
.axiOut_1_bready ( axiOut_1_bready ),
|
||
.axiOut_1_bvalid ( axiOut_1_bvalid ),
|
||
.axiOut_1_bid ( axiOut_1_bid ),
|
||
.axiOut_1_bresp ( axiOut_1_bresp ),
|
||
//ar
|
||
.axiOut_1_arvalid ( axiOut_1_arvalid ),
|
||
.axiOut_1_arready ( axiOut_1_arready ),
|
||
.axiOut_1_araddr ( axiOut_1_araddr ),
|
||
.axiOut_1_arid ( axiOut_1_arid ),
|
||
.axiOut_1_arlen ( axiOut_1_arlen ),
|
||
.axiOut_1_arsize ( axiOut_1_arsize ),
|
||
.axiOut_1_arburst ( axiOut_1_arburst ),
|
||
.axiOut_1_arlock ( axiOut_1_arlock ),
|
||
.axiOut_1_arcache ( axiOut_1_arcache ),
|
||
.axiOut_1_arprot ( axiOut_1_arprot ),
|
||
//r
|
||
.axiOut_1_rvalid ( axiOut_1_rvalid ),
|
||
.axiOut_1_rready ( axiOut_1_rready ),
|
||
.axiOut_1_rdata ( axiOut_1_rdata ),
|
||
.axiOut_1_rid ( axiOut_1_rid ),
|
||
.axiOut_1_rresp ( axiOut_1_rresp ),
|
||
.axiOut_1_rlast ( axiOut_1_rlast ),
|
||
|
||
//slave 2
|
||
//aw
|
||
.axiOut_2_awvalid ( uart_awvalid ),
|
||
.axiOut_2_awready ( uart_awready ),
|
||
.axiOut_2_awaddr ( uart_awaddr ),
|
||
.axiOut_2_awid ( uart_awid ),
|
||
.axiOut_2_awlen ( uart_awlen ),
|
||
.axiOut_2_awsize ( uart_awsize ),
|
||
.axiOut_2_awburst ( uart_awburst ),
|
||
.axiOut_2_awlock ( uart_awlock ),
|
||
.axiOut_2_awcache ( uart_awcache ),
|
||
.axiOut_2_awprot ( uart_awprot ),
|
||
//w
|
||
.axiOut_2_wvalid ( uart_wvalid ),
|
||
.axiOut_2_wready ( uart_wready ),
|
||
.axiOut_2_wdata ( uart_wdata ),
|
||
.axiOut_2_wstrb ( uart_wstrb ),
|
||
.axiOut_2_wlast ( uart_wlast ),
|
||
//b
|
||
.axiOut_2_bready ( uart_bready ),
|
||
.axiOut_2_bvalid ( uart_bvalid ),
|
||
.axiOut_2_bid ( uart_bid ),
|
||
.axiOut_2_bresp ( uart_bresp ),
|
||
//ar
|
||
.axiOut_2_arvalid ( uart_arvalid ),
|
||
.axiOut_2_arready ( uart_arready ),
|
||
.axiOut_2_araddr ( uart_araddr ),
|
||
.axiOut_2_arid ( uart_arid ),
|
||
.axiOut_2_arlen ( uart_arlen ),
|
||
.axiOut_2_arsize ( uart_arsize ),
|
||
.axiOut_2_arburst ( uart_arburst ),
|
||
.axiOut_2_arlock ( uart_arlock ),
|
||
.axiOut_2_arcache ( uart_arcache ),
|
||
.axiOut_2_arprot ( uart_arprot ),
|
||
//r
|
||
.axiOut_2_rvalid ( uart_rvalid ),
|
||
.axiOut_2_rready ( uart_rready ),
|
||
.axiOut_2_rdata ( uart_rdata ),
|
||
.axiOut_2_rid ( uart_rid ),
|
||
.axiOut_2_rresp ( uart_rresp ),
|
||
.axiOut_2_rlast ( uart_rlast ),
|
||
|
||
//slave 3
|
||
//aw
|
||
.axiOut_3_awvalid ( dvi_awvalid ),
|
||
.axiOut_3_awready ( dvi_awready ),
|
||
.axiOut_3_awaddr ( dvi_awaddr ),
|
||
.axiOut_3_awid ( dvi_awid ),
|
||
.axiOut_3_awlen ( dvi_awlen ),
|
||
.axiOut_3_awsize ( dvi_awsize ),
|
||
.axiOut_3_awburst ( dvi_awburst ),
|
||
.axiOut_3_awlock ( dvi_awlock ),
|
||
.axiOut_3_awcache ( dvi_awcache ),
|
||
.axiOut_3_awprot ( dvi_awprot ),
|
||
//w
|
||
.axiOut_3_wvalid ( dvi_wvalid ),
|
||
.axiOut_3_wready ( dvi_wready ),
|
||
.axiOut_3_wdata ( dvi_wdata ),
|
||
.axiOut_3_wstrb ( dvi_wstrb ),
|
||
.axiOut_3_wlast ( dvi_wlast ),
|
||
//b
|
||
.axiOut_3_bready ( dvi_bready ),
|
||
.axiOut_3_bvalid ( dvi_bvalid ),
|
||
.axiOut_3_bid ( dvi_bid ),
|
||
.axiOut_3_bresp ( dvi_bresp ),
|
||
//ar
|
||
.axiOut_3_arvalid ( dvi_arvalid ),
|
||
.axiOut_3_arready ( dvi_arready ),
|
||
.axiOut_3_araddr ( dvi_araddr ),
|
||
.axiOut_3_arid ( dvi_arid ),
|
||
.axiOut_3_arlen ( dvi_arlen ),
|
||
.axiOut_3_arsize ( dvi_arsize ),
|
||
.axiOut_3_arburst ( dvi_arburst ),
|
||
.axiOut_3_arlock ( dvi_arlock ),
|
||
.axiOut_3_arcache ( dvi_arcache ),
|
||
.axiOut_3_arprot ( dvi_arprot ),
|
||
//r
|
||
.axiOut_3_rvalid ( dvi_rvalid ),
|
||
.axiOut_3_rready ( dvi_rready ),
|
||
.axiOut_3_rdata ( dvi_rdata ),
|
||
.axiOut_3_rid ( dvi_rid ),
|
||
.axiOut_3_rresp ( dvi_rresp ),
|
||
.axiOut_3_rlast ( dvi_rlast ),
|
||
|
||
|
||
//slave 4
|
||
//aw
|
||
.axiOut_4_awvalid ( confreg_awvalid ),
|
||
.axiOut_4_awready ( confreg_awready ),
|
||
.axiOut_4_awaddr ( confreg_awaddr ),
|
||
.axiOut_4_awid ( confreg_awid ),
|
||
.axiOut_4_awlen ( confreg_awlen ),
|
||
.axiOut_4_awsize ( confreg_awsize ),
|
||
.axiOut_4_awburst ( confreg_awburst ),
|
||
.axiOut_4_awlock ( confreg_awlock ),
|
||
.axiOut_4_awcache ( confreg_awcache ),
|
||
.axiOut_4_awprot ( confreg_awprot ),
|
||
//w
|
||
.axiOut_4_wvalid ( confreg_wvalid ),
|
||
.axiOut_4_wready ( confreg_wready ),
|
||
.axiOut_4_wdata ( confreg_wdata ),
|
||
.axiOut_4_wstrb ( confreg_wstrb ),
|
||
.axiOut_4_wlast ( confreg_wlast ),
|
||
//b
|
||
.axiOut_4_bready ( confreg_bready ),
|
||
.axiOut_4_bvalid ( confreg_bvalid ),
|
||
.axiOut_4_bid ( confreg_bid ),
|
||
.axiOut_4_bresp ( confreg_bresp ),
|
||
//ar
|
||
.axiOut_4_arvalid ( confreg_arvalid ),
|
||
.axiOut_4_arready ( confreg_arready ),
|
||
.axiOut_4_araddr ( confreg_araddr ),
|
||
.axiOut_4_arid ( confreg_arid ),
|
||
.axiOut_4_arlen ( confreg_arlen ),
|
||
.axiOut_4_arsize ( confreg_arsize ),
|
||
.axiOut_4_arburst ( confreg_arburst ),
|
||
.axiOut_4_arlock ( confreg_arlock ),
|
||
.axiOut_4_arcache ( confreg_arcache ),
|
||
.axiOut_4_arprot ( confreg_arprot ),
|
||
//r
|
||
.axiOut_4_rvalid ( confreg_rvalid ),
|
||
.axiOut_4_rready ( confreg_rready ),
|
||
.axiOut_4_rdata ( confreg_rdata ),
|
||
.axiOut_4_rid ( confreg_rid ),
|
||
.axiOut_4_rresp ( confreg_rresp ),
|
||
.axiOut_4_rlast ( confreg_rlast ),
|
||
|
||
//slave 5
|
||
//aw
|
||
.axiOut_5_awvalid ( dma_s_awvalid ),
|
||
.axiOut_5_awready ( dma_s_awready ),
|
||
.axiOut_5_awaddr ( dma_s_awaddr ),
|
||
.axiOut_5_awid ( dma_s_awid ),
|
||
.axiOut_5_awlen ( dma_s_awlen ),
|
||
.axiOut_5_awsize ( dma_s_awsize ),
|
||
.axiOut_5_awburst ( dma_s_awburst ),
|
||
.axiOut_5_awlock ( dma_s_awlock ),
|
||
.axiOut_5_awcache ( dma_s_awcache ),
|
||
.axiOut_5_awprot ( dma_s_awprot ),
|
||
//w
|
||
.axiOut_5_wvalid ( dma_s_wvalid ),
|
||
.axiOut_5_wready ( dma_s_wready ),
|
||
.axiOut_5_wdata ( dma_s_wdata ),
|
||
.axiOut_5_wstrb ( dma_s_wstrb ),
|
||
.axiOut_5_wlast ( dma_s_wlast ),
|
||
//b
|
||
.axiOut_5_bready ( dma_s_bready ),
|
||
.axiOut_5_bvalid ( dma_s_bvalid ),
|
||
.axiOut_5_bid ( dma_s_bid ),
|
||
.axiOut_5_bresp ( dma_s_bresp ),
|
||
//ar
|
||
.axiOut_5_arvalid ( dma_s_arvalid ),
|
||
.axiOut_5_arready ( dma_s_arready ),
|
||
.axiOut_5_araddr ( dma_s_araddr ),
|
||
.axiOut_5_arid ( dma_s_arid ),
|
||
.axiOut_5_arlen ( dma_s_arlen ),
|
||
.axiOut_5_arsize ( dma_s_arsize ),
|
||
.axiOut_5_arburst ( dma_s_arburst ),
|
||
.axiOut_5_arlock ( dma_s_arlock ),
|
||
.axiOut_5_arcache ( dma_s_arcache ),
|
||
.axiOut_5_arprot ( dma_s_arprot ),
|
||
//r
|
||
.axiOut_5_rvalid ( dma_s_rvalid ),
|
||
.axiOut_5_rready ( dma_s_rready ),
|
||
.axiOut_5_rdata ( dma_s_rdata ),
|
||
.axiOut_5_rid ( dma_s_rid ),
|
||
.axiOut_5_rresp ( dma_s_rresp ),
|
||
.axiOut_5_rlast ( dma_s_rlast ),
|
||
|
||
//slave 6
|
||
//aw
|
||
.axiOut_6_awvalid ( fft_awvalid ),
|
||
.axiOut_6_awready ( fft_awready ),
|
||
.axiOut_6_awaddr ( fft_awaddr ),
|
||
.axiOut_6_awid ( fft_awid ),
|
||
.axiOut_6_awlen ( fft_awlen ),
|
||
.axiOut_6_awsize ( fft_awsize ),
|
||
.axiOut_6_awburst ( fft_awburst ),
|
||
.axiOut_6_awlock ( fft_awlock ),
|
||
.axiOut_6_awcache ( fft_awcache ),
|
||
.axiOut_6_awprot ( fft_awprot ),
|
||
//w
|
||
.axiOut_6_wvalid ( fft_wvalid ),
|
||
.axiOut_6_wready ( fft_wready ),
|
||
.axiOut_6_wdata ( fft_wdata ),
|
||
.axiOut_6_wstrb ( fft_wstrb ),
|
||
.axiOut_6_wlast ( fft_wlast ),
|
||
//b
|
||
.axiOut_6_bready ( fft_bready ),
|
||
.axiOut_6_bvalid ( fft_bvalid ),
|
||
.axiOut_6_bid ( fft_bid ),
|
||
.axiOut_6_bresp ( fft_bresp ),
|
||
//ar
|
||
.axiOut_6_arvalid ( fft_arvalid ),
|
||
.axiOut_6_arready ( fft_arready ),
|
||
.axiOut_6_araddr ( fft_araddr ),
|
||
.axiOut_6_arid ( fft_arid ),
|
||
.axiOut_6_arlen ( fft_arlen ),
|
||
.axiOut_6_arsize ( fft_arsize ),
|
||
.axiOut_6_arburst ( fft_arburst ),
|
||
.axiOut_6_arlock ( fft_arlock ),
|
||
.axiOut_6_arcache ( fft_arcache ),
|
||
.axiOut_6_arprot ( fft_arprot ),
|
||
//r
|
||
.axiOut_6_rvalid ( fft_rvalid ),
|
||
.axiOut_6_rready ( fft_rready ),
|
||
.axiOut_6_rdata ( fft_rdata ),
|
||
.axiOut_6_rid ( fft_rid ),
|
||
.axiOut_6_rresp ( fft_rresp ),
|
||
.axiOut_6_rlast ( fft_rlast ),
|
||
|
||
//slave 7
|
||
//aw
|
||
.axiOut_7_awvalid ( axiOut_7_awvalid ),
|
||
.axiOut_7_awready ( axiOut_7_awready ),
|
||
.axiOut_7_awaddr ( axiOut_7_awaddr ),
|
||
.axiOut_7_awid ( axiOut_7_awid ),
|
||
.axiOut_7_awlen ( axiOut_7_awlen ),
|
||
.axiOut_7_awsize ( axiOut_7_awsize ),
|
||
.axiOut_7_awburst ( axiOut_7_awburst ),
|
||
.axiOut_7_awlock ( axiOut_7_awlock ),
|
||
.axiOut_7_awcache ( axiOut_7_awcache ),
|
||
.axiOut_7_awprot ( axiOut_7_awprot ),
|
||
//w
|
||
.axiOut_7_wvalid ( axiOut_7_wvalid ),
|
||
.axiOut_7_wready ( axiOut_7_wready ),
|
||
.axiOut_7_wdata ( axiOut_7_wdata ),
|
||
.axiOut_7_wstrb ( axiOut_7_wstrb ),
|
||
.axiOut_7_wlast ( axiOut_7_wlast ),
|
||
//b
|
||
.axiOut_7_bready ( axiOut_7_bready ),
|
||
.axiOut_7_bvalid ( axiOut_7_bvalid ),
|
||
.axiOut_7_bid ( axiOut_7_bid ),
|
||
.axiOut_7_bresp ( axiOut_7_bresp ),
|
||
//ar
|
||
.axiOut_7_arvalid ( axiOut_7_arvalid ),
|
||
.axiOut_7_arready ( axiOut_7_arready ),
|
||
.axiOut_7_araddr ( axiOut_7_araddr ),
|
||
.axiOut_7_arid ( axiOut_7_arid ),
|
||
.axiOut_7_arlen ( axiOut_7_arlen ),
|
||
.axiOut_7_arsize ( axiOut_7_arsize ),
|
||
.axiOut_7_arburst ( axiOut_7_arburst ),
|
||
.axiOut_7_arlock ( axiOut_7_arlock ),
|
||
.axiOut_7_arcache ( axiOut_7_arcache ),
|
||
.axiOut_7_arprot ( axiOut_7_arprot ),
|
||
//r
|
||
.axiOut_7_rvalid ( axiOut_7_rvalid ),
|
||
.axiOut_7_rready ( axiOut_7_rready ),
|
||
.axiOut_7_rdata ( axiOut_7_rdata ),
|
||
.axiOut_7_rid ( axiOut_7_rid ),
|
||
.axiOut_7_rresp ( axiOut_7_rresp ),
|
||
.axiOut_7_rlast ( axiOut_7_rlast )
|
||
|
||
);
|
||
|
||
// add your code
|
||
|
||
endmodule
|
||
|