FallenSigh 660447380c feat(ip): add BRAM IP core

2026-04-12 22:23:25 +08:00

.spec-workflow

initial commit

2026-04-12 22:20:18 +08:00

doc

initial commit

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fpga

build(script): add bitstream copy automation script

2026-04-12 22:21:21 +08:00

rtl

feat(ip): add BRAM IP core

2026-04-12 22:23:25 +08:00

sdk/software

initial commit

2026-04-12 22:20:18 +08:00

sim

initial commit

2026-04-12 22:20:18 +08:00

.gitattributes

initial commit

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.gitignore

initial commit

2026-04-12 22:20:18 +08:00

Description

2026年全国大学生集成电路创新创业大赛（CICC） “龙芯中科”企业命题的参赛代码仓库

13 MiB

Languages

Verilog 73.9%

C 20%

SystemVerilog 4.3%

Tcl 1.2%

Makefile 0.6%