55 lines
1.3 KiB
Verilog
55 lines
1.3 KiB
Verilog
module fpga_sram_sp #(
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parameter AW = 16,
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parameter Init_File = "none"
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)
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(
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input wire CLK,
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input wire [AW-1:0] ADDR,
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input wire [31:0] WDATA,
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input wire [3:0] WREN,
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input wire CS,
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output wire [31:0] RDATA
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);
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localparam AWT = ((1<<(AW-0))-1);
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localparam V_STYLE = "block";
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localparam P_STYLE = (V_STYLE == "ultra") ? "uram" :
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(V_STYLE == "distributed") ? "select_ram" :
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"block_ram";
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(*ram_style = V_STYLE*)reg [31:0] BRAM [AWT:0]/*synthesis syn_ramstyle=P_STYLE*/;
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initial begin
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if(Init_File != "none") begin
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$readmemb(Init_File,BRAM);
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end
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end
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reg [AW-1:0] addr_q1;
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wire [3:0] write_enable;
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assign write_enable[3:0] = WREN[3:0] & {4{CS}};
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always@(posedge CLK) begin
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if(write_enable[0]) BRAM[ADDR][7:0] <= WDATA[7:0];
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end
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always@(posedge CLK) begin
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if(write_enable[1]) BRAM[ADDR][15:8] <= WDATA[15:8];
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end
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always@(posedge CLK) begin
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if(write_enable[2]) BRAM[ADDR][23:16] <= WDATA[23:16];
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end
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always@(posedge CLK) begin
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if(write_enable[3]) BRAM[ADDR][31:24] <= WDATA[31:24];
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end
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always @ (posedge CLK) begin
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if(CS && !(|WREN))
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addr_q1 <= ADDR[AW-1:0];
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end
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assign RDATA = BRAM[addr_q1];
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endmodule
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