FallenSigh 1a51b3f67b fix(sim): fix simulation errors

2026-04-14 01:22:34 +08:00

doc

initial commit

2026-04-12 22:20:18 +08:00

fpga

build(tcl): add bram0.xci to create_project script

2026-04-12 22:24:19 +08:00

rtl

fix(sim): fix simulation errors

2026-04-14 01:22:34 +08:00

sdk/software

test: add test results for fft, dma, fft_dma

2026-04-13 17:27:15 +08:00

sim

fix(sim): fix simulation errors

2026-04-14 01:22:34 +08:00

.gitattributes

initial commit

2026-04-12 22:20:18 +08:00

.gitignore

chore(git): remove spec-workflow and ignore it

2026-04-12 22:30:15 +08:00

Description

2026年全国大学生集成电路创新创业大赛（CICC） “龙芯中科”企业命题的参赛代码仓库

13 MiB

Languages

Verilog 73.9%

C 20%

SystemVerilog 4.3%

Tcl 1.2%

Makefile 0.6%