FallenSigh 1a51b3f67b fix(sim): fix simulation errors

2026-04-14 01:22:34 +08:00

..

APB_UART

initial commit

2026-04-12 22:20:18 +08:00

axi_axil_adapter

fix(sim): fix simulation errors

2026-04-14 01:22:34 +08:00

bram0

feat(ip): add BRAM IP core

2026-04-12 22:23:25 +08:00

Bus_interconnects

initial commit

2026-04-12 22:20:18 +08:00

cdma

fix(sim): fix simulation errors

2026-04-14 01:22:34 +08:00

confreg

feat(confreg): add interrupt support for fft, dma and uart

2026-04-13 00:11:31 +08:00

DVI

fix(sim): fix simulation errors

2026-04-14 01:22:34 +08:00

fft

feat(ip): integrate 1024-point AXI FFT IP

2026-04-12 22:26:20 +08:00

open-la500

initial commit

2026-04-12 22:20:18 +08:00

PLL_2018_3

initial commit

2026-04-12 22:20:18 +08:00

PLL_2019_2

initial commit

2026-04-12 22:20:18 +08:00

PLL_2023_2

initial commit

2026-04-12 22:20:18 +08:00

ram_wrap

initial commit

2026-04-12 22:20:18 +08:00

rst_sync

initial commit

2026-04-12 22:20:18 +08:00