fix(sim): fix simulation errors

2026-04-14 01:22:34 +08:00
parent d082f9e3d2
commit 1a51b3f67b
7 changed files with 61 additions and 48 deletions
--- a/sim/mycpu_tb.v
+++ b/sim/mycpu_tb.v
@@ -184,12 +184,7 @@ always @(posedge clk)
 begin
    if(uart_display)
    begin
-        if(uart_data==8'hff)
-        begin
-            ;//$finish;
-        end
-        else
-        begin
+        if(uart_data !=8'hff) begin
            $write("%c",uart_data);
        end
    end