From 1a51b3f67be783e10856bdc76c6c766c7d78b971 Mon Sep 17 00:00:00 2001 From: FallenSigh Date: Tue, 14 Apr 2026 01:22:34 +0800 Subject: [PATCH] fix(sim): fix simulation errors --- rtl/ip/DVI/axi_dvi.v | 14 +++---- rtl/ip/axi_axil_adapter/axi_axil_adapter_rd.v | 14 +++++-- rtl/ip/axi_axil_adapter/axi_axil_adapter_wr.v | 24 +++++++----- rtl/ip/cdma/snix_axil_cdma_mux.sv | 7 +++- rtl/soc_top.v | 6 ++- sim/mycpu_tb.v | 7 +--- sim/sram.v | 37 +++++++++++-------- 7 files changed, 61 insertions(+), 48 deletions(-) diff --git a/rtl/ip/DVI/axi_dvi.v b/rtl/ip/DVI/axi_dvi.v index b77b165..26ec9dd 100644 --- a/rtl/ip/DVI/axi_dvi.v +++ b/rtl/ip/DVI/axi_dvi.v @@ -24,11 +24,11 @@ module axi_dvi # input [3:0] s_awcache, input [2:0] s_awprot, input s_wvalid, - output s_wready, + output reg s_wready, input [31:0] s_wdata, input [3:0] s_wstrb, input s_wlast, - output s_bvalid, + output reg s_bvalid, input s_bready, output [4:0] s_bid, output [1:0] s_bresp, @@ -42,12 +42,12 @@ module axi_dvi # input [0:0] s_arlock, input [3:0] s_arcache, input [2:0] s_arprot, - output s_rvalid, + output reg s_rvalid, input s_rready, - output [31:0] s_rdata, + output reg [31:0] s_rdata, output [4:0] s_rid, output [1:0] s_rresp, - output s_rlast, + output reg s_rlast, output video_clk, // Video clock signal output hsync, // Horizontal sync signal @@ -64,7 +64,6 @@ module axi_dvi # reg [31:0] DVI_RECT_DIR,DVI_RECT_L_W,DVI_SQU_DIR,DVI_SQU_R; reg busy,write,R_or_W; - reg s_wready; wire ar_enter = s_arvalid & s_arready; wire r_retire = s_rvalid & s_rready & s_rlast; @@ -126,8 +125,6 @@ module axi_dvi # else if(w_enter & s_wlast) s_wready <= 1'b0; - reg [31:0] s_rdata; - reg s_rvalid,s_rlast; wire [31:0] rdata_d = buf_addr[15:0] == 16'h0 ? DVI_RECT_DIR : buf_addr[15:0] == 16'h4 ? DVI_RECT_L_W : buf_addr[15:0] == 16'h8 ? DVI_SQU_DIR : @@ -152,7 +149,6 @@ module axi_dvi # end end - reg s_bvalid; always@(posedge aclk) begin if(~aresetn) s_bvalid <= 1'b0; else if(w_enter) s_bvalid <= 1'b1; diff --git a/rtl/ip/axi_axil_adapter/axi_axil_adapter_rd.v b/rtl/ip/axi_axil_adapter/axi_axil_adapter_rd.v index 8faf535..e27dfa4 100644 --- a/rtl/ip/axi_axil_adapter/axi_axil_adapter_rd.v +++ b/rtl/ip/axi_axil_adapter/axi_axil_adapter_rd.v @@ -134,6 +134,12 @@ initial begin end end +localparam SAFE_EXP_MSB = (AXIL_ADDR_BIT_OFFSET > AXI_ADDR_BIT_OFFSET) ? AXIL_ADDR_BIT_OFFSET - 1 : AXI_ADDR_BIT_OFFSET; +localparam SAFE_EXP_LSB = AXI_ADDR_BIT_OFFSET; + +localparam SAFE_NAR_MSB = (AXI_ADDR_BIT_OFFSET > AXIL_ADDR_BIT_OFFSET) ? AXI_ADDR_BIT_OFFSET - 1 : AXIL_ADDR_BIT_OFFSET; +localparam SAFE_NAR_LSB = AXIL_ADDR_BIT_OFFSET; + localparam [1:0] STATE_IDLE = 2'd0, STATE_DATA = 2'd1, @@ -286,7 +292,7 @@ always @* begin if (m_axil_rready && m_axil_rvalid) begin s_axi_rid_next = id_reg; - s_axi_rdata_next = m_axil_rdata >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH); + s_axi_rdata_next = m_axil_rdata >> (addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB] * AXI_DATA_WIDTH); s_axi_rresp_next = m_axil_rresp; s_axi_rlast_next = 1'b0; s_axi_rvalid_next = 1'b1; @@ -316,7 +322,7 @@ always @* begin s_axi_rid_next = id_reg; data_next = m_axil_rdata; resp_next = m_axil_rresp; - s_axi_rdata_next = m_axil_rdata >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH); + s_axi_rdata_next = m_axil_rdata >> (addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB] * AXI_DATA_WIDTH); s_axi_rresp_next = m_axil_rresp; s_axi_rlast_next = 1'b0; s_axi_rvalid_next = 1'b1; @@ -346,7 +352,7 @@ always @* begin if (s_axi_rready || !s_axi_rvalid) begin s_axi_rid_next = id_reg; - s_axi_rdata_next = data_reg >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH); + s_axi_rdata_next = data_reg >> (addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB] * AXI_DATA_WIDTH); s_axi_rresp_next = resp_reg; s_axi_rlast_next = 1'b0; s_axi_rvalid_next = 1'b1; @@ -412,7 +418,7 @@ always @* begin m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid; if (m_axil_rready && m_axil_rvalid) begin - data_next[addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axil_rdata; + data_next[addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axil_rdata; if (m_axil_rresp) begin resp_next = m_axil_rresp; end diff --git a/rtl/ip/axi_axil_adapter/axi_axil_adapter_wr.v b/rtl/ip/axi_axil_adapter/axi_axil_adapter_wr.v index 52d4be2..44822d5 100644 --- a/rtl/ip/axi_axil_adapter/axi_axil_adapter_wr.v +++ b/rtl/ip/axi_axil_adapter/axi_axil_adapter_wr.v @@ -146,6 +146,12 @@ localparam [1:0] STATE_DATA_2 = 2'd2, STATE_RESP = 2'd3; +// 添加安全的位选边界，防止 ModelSim 报 Range Reversed 错误 +localparam SAFE_EXP_MSB = (AXIL_ADDR_BIT_OFFSET > AXI_ADDR_BIT_OFFSET) ? AXIL_ADDR_BIT_OFFSET - 1 : AXI_ADDR_BIT_OFFSET; +localparam SAFE_EXP_LSB = AXI_ADDR_BIT_OFFSET; + +localparam SAFE_NAR_MSB = (AXI_ADDR_BIT_OFFSET > AXIL_ADDR_BIT_OFFSET) ? AXI_ADDR_BIT_OFFSET - 1 : AXIL_ADDR_BIT_OFFSET; +localparam SAFE_NAR_LSB = AXIL_ADDR_BIT_OFFSET; reg [1:0] state_reg = STATE_IDLE, state_next; reg [AXI_ID_WIDTH-1:0] id_reg = {AXI_ID_WIDTH{1'b0}}, id_next; @@ -335,7 +341,7 @@ always @* begin if (s_axi_wready && s_axi_wvalid) begin m_axil_wdata_next = {(AXIL_WORD_WIDTH/AXI_WORD_WIDTH){s_axi_wdata}}; - m_axil_wstrb_next = s_axi_wstrb << (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_STRB_WIDTH); + m_axil_wstrb_next = s_axi_wstrb << (addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB] * AXI_STRB_WIDTH); m_axil_wvalid_next = 1'b1; burst_next = burst_reg - 1; burst_active_next = burst_reg != 0; @@ -354,13 +360,13 @@ always @* begin if (CONVERT_NARROW_BURST) begin for (i = 0; i < AXI_WORD_WIDTH; i = i + 1) begin if (s_axi_wstrb[i]) begin - data_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH+i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE] = s_axi_wdata[i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE]; - strb_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH+i] = 1'b1; + data_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_DATA_WIDTH+i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE] = s_axi_wdata[i*AXIL_WORD_SIZE +: AXIL_WORD_SIZE]; + strb_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_STRB_WIDTH+i] = 1'b1; end end end else begin - data_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = s_axi_wdata; - strb_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEGMENT_STRB_WIDTH +: SEGMENT_STRB_WIDTH] = s_axi_wstrb; + data_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = s_axi_wdata; + strb_next[addr_reg[SAFE_EXP_MSB:SAFE_EXP_LSB]*SEGMENT_STRB_WIDTH +: SEGMENT_STRB_WIDTH] = s_axi_wstrb; end m_axil_wdata_next = data_next; m_axil_wstrb_next = strb_next; @@ -451,8 +457,8 @@ always @* begin if (s_axi_wready && s_axi_wvalid) begin data_next = s_axi_wdata; strb_next = s_axi_wstrb; - m_axil_wdata_next = s_axi_wdata >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_WIDTH); - m_axil_wstrb_next = s_axi_wstrb >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_WIDTH); + m_axil_wdata_next = s_axi_wdata >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_DATA_WIDTH); + m_axil_wstrb_next = s_axi_wstrb >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_STRB_WIDTH); m_axil_wvalid_next = 1'b1; burst_next = burst_reg - 1; burst_active_next = burst_reg != 0; @@ -469,8 +475,8 @@ always @* begin s_axi_wready_next = 1'b0; if (!m_axil_wvalid || m_axil_wready) begin - m_axil_wdata_next = data_reg >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_WIDTH); - m_axil_wstrb_next = strb_reg >> (addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_WIDTH); + m_axil_wdata_next = data_reg >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_DATA_WIDTH); + m_axil_wstrb_next = strb_reg >> (addr_reg[SAFE_NAR_MSB:SAFE_NAR_LSB] * AXIL_STRB_WIDTH); m_axil_wvalid_next = 1'b1; addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_WIDTH{1'b1}} << master_burst_size_reg); last_segment_next = addr_next[burst_size_reg] != addr_reg[burst_size_reg]; diff --git a/rtl/ip/cdma/snix_axil_cdma_mux.sv b/rtl/ip/cdma/snix_axil_cdma_mux.sv index ff004fe..ba82421 100644 --- a/rtl/ip/cdma/snix_axil_cdma_mux.sv +++ b/rtl/ip/cdma/snix_axil_cdma_mux.sv @@ -305,9 +305,12 @@ module snix_axil_cdma_mux #( case (state) IDLE: begin for (int i = 0; i < PORTS; i++) begin + logic [CH_BITS:0] check_ch_ext; + logic [CH_BITS-1:0] check_ch; + // Calculate next channel safely avoiding modulo operators in loop - logic [CH_BITS:0] check_ch_ext = {1'b0, rr_ptr} + i[CH_BITS:0]; - logic [CH_BITS-1:0] check_ch = (check_ch_ext >= PORTS) ? (check_ch_ext - PORTS) : check_ch_ext[CH_BITS-1:0]; + check_ch_ext = {1'b0, rr_ptr} + i[CH_BITS:0]; + check_ch = (check_ch_ext >= PORTS) ? (check_ch_ext - PORTS) : check_ch_ext[CH_BITS-1:0]; if (ch_req[check_ch] && !arb_set_done[check_ch]) begin cur_ch <= check_ch; diff --git a/rtl/soc_top.v b/rtl/soc_top.v index 91abc5d..f8bdac8 100644 --- a/rtl/soc_top.v +++ b/rtl/soc_top.v @@ -30,6 +30,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -------------------------------------------------------------------------------- ------------------------------------------------------------------------------*/ +`timescale 1ns / 1ps + //1f00_0000 apb //1f10_0000 dvi //1f20_0000 confreg @@ -1571,8 +1573,8 @@ snix_axil_cdma_mux #( .AXIL_DATA_WIDTH (32), .ID_WIDTH (4), // 匹配 Crossbar 的 Master ID 宽度 .USER_WIDTH (1), - .PORTS (8), - .FIFO_DEPTH (64) // 8 个独立通道 + .PORTS (4), // 8 个通道 + .FIFO_DEPTH (64) ) u_snix_axil_cdma_mux_8ch ( .clk (sys_clk), .rst_n (sys_resetn), // 低电平复位 diff --git a/sim/mycpu_tb.v b/sim/mycpu_tb.v index d2846ef..d7bf9fa 100644 --- a/sim/mycpu_tb.v +++ b/sim/mycpu_tb.v @@ -184,12 +184,7 @@ always @(posedge clk) begin if(uart_display) begin - if(uart_data==8'hff) - begin - ;//$finish; - end - else - begin + if(uart_data !=8'hff) begin $write("%c",uart_data); end end diff --git a/sim/sram.v b/sim/sram.v index 8f2ace7..850c262 100644 --- a/sim/sram.v +++ b/sim/sram.v @@ -27,23 +27,28 @@ module sram_sp #( assign write_enable[3:0] = (~ram_be_n) & {4{(~ram_ce_n) & (~ram_we_n)}}; - - always@(posedge write_enable[0]) begin - #10; - if(~ram_be_n[0]) BRAM[ram_addr][7:0] <= ram_data[7:0]; - end - always@(posedge write_enable[1]) begin - #10; - if(~ram_be_n[1]) BRAM[ram_addr][15:8] <= ram_data[15:8]; - end - always@(posedge write_enable[2]) begin - #10; - if(~ram_be_n[2]) BRAM[ram_addr][23:16] <= ram_data[23:16]; - end - always@(posedge write_enable[3]) begin - #10; - if(~ram_be_n[3]) BRAM[ram_addr][31:24] <= ram_data[31:24]; + always @(*) begin + if (write_enable[0]) BRAM[ram_addr][7:0] = ram_data[7:0]; + if (write_enable[1]) BRAM[ram_addr][15:8] = ram_data[15:8]; + if (write_enable[2]) BRAM[ram_addr][23:16] = ram_data[23:16]; + if (write_enable[3]) BRAM[ram_addr][31:24] = ram_data[31:24]; end + // always@(posedge write_enable[0]) begin + // #10; + // if(~ram_be_n[0]) BRAM[ram_addr][7:0] <= ram_data[7:0]; + // end + // always@(posedge write_enable[1]) begin + // #10; + // if(~ram_be_n[1]) BRAM[ram_addr][15:8] <= ram_data[15:8]; + // end + // always@(posedge write_enable[2]) begin + // #10; + // if(~ram_be_n[2]) BRAM[ram_addr][23:16] <= ram_data[23:16]; + // end + // always@(posedge write_enable[3]) begin + // #10; + // if(~ram_be_n[3]) BRAM[ram_addr][31:24] <= ram_data[31:24]; + // end wire [31:0] RDATA = BRAM[ram_addr];