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fix(sim): fix simulation errors

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FallenSigh
2026-04-14 01:22:34 +08:00
parent d082f9e3d2
commit 1a51b3f67b
7 changed files with 61 additions and 48 deletions
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7
sim/mycpu_tb.v
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@@ -184,12 +184,7 @@ always @(posedge clk)
begin
if(uart_display)
begin
if(uart_data==8'hff)
begin
;//$finish;
end
else
begin
if(uart_data !=8'hff) begin
$write("%c",uart_data);
end
end

37
sim/sram.v
View File

@@ -27,23 +27,28 @@ module sram_sp #(
assign write_enable[3:0] = (~ram_be_n) & {4{(~ram_ce_n) & (~ram_we_n)}};
always@(posedge write_enable[0]) begin
#10;
if(~ram_be_n[0]) BRAM[ram_addr][7:0] <= ram_data[7:0];
end
always@(posedge write_enable[1]) begin
#10;
if(~ram_be_n[1]) BRAM[ram_addr][15:8] <= ram_data[15:8];
end
always@(posedge write_enable[2]) begin
#10;
if(~ram_be_n[2]) BRAM[ram_addr][23:16] <= ram_data[23:16];
end
always@(posedge write_enable[3]) begin
#10;
if(~ram_be_n[3]) BRAM[ram_addr][31:24] <= ram_data[31:24];
always @(*) begin
if (write_enable[0]) BRAM[ram_addr][7:0] = ram_data[7:0];
if (write_enable[1]) BRAM[ram_addr][15:8] = ram_data[15:8];
if (write_enable[2]) BRAM[ram_addr][23:16] = ram_data[23:16];
if (write_enable[3]) BRAM[ram_addr][31:24] = ram_data[31:24];
end
// always@(posedge write_enable[0]) begin
// #10;
// if(~ram_be_n[0]) BRAM[ram_addr][7:0] <= ram_data[7:0];
// end
// always@(posedge write_enable[1]) begin
// #10;
// if(~ram_be_n[1]) BRAM[ram_addr][15:8] <= ram_data[15:8];
// end
// always@(posedge write_enable[2]) begin
// #10;
// if(~ram_be_n[2]) BRAM[ram_addr][23:16] <= ram_data[23:16];
// end
// always@(posedge write_enable[3]) begin
// #10;
// if(~ram_be_n[3]) BRAM[ram_addr][31:24] <= ram_data[31:24];
// end
wire [31:0] RDATA = BRAM[ram_addr];