fallensigh/ciciec2026_loongson
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fix(sim): fix simulation errors

Browse Source
This commit is contained in:
FallenSigh
2026-04-14 01:22:34 +08:00
parent d082f9e3d2
commit 1a51b3f67b
7 changed files with 61 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
rtl/ip/DVI/axi_dvi.v
View File

@@ -24,11 +24,11 @@ module axi_dvi #
input [3:0] s_awcache,
input [2:0] s_awprot,
input s_wvalid,
output s_wready,
output reg s_wready,
input [31:0] s_wdata,
input [3:0] s_wstrb,
input s_wlast,
output s_bvalid,
output reg s_bvalid,
input s_bready,
output [4:0] s_bid,
output [1:0] s_bresp,
@@ -42,12 +42,12 @@ module axi_dvi #
input [0:0] s_arlock,
input [3:0] s_arcache,
input [2:0] s_arprot,
output s_rvalid,
output reg s_rvalid,
input s_rready,
output [31:0] s_rdata,
output reg [31:0] s_rdata,
output [4:0] s_rid,
output [1:0] s_rresp,
output s_rlast,
output reg s_rlast,
output video_clk, // Video clock signal
output hsync, // Horizontal sync signal
@@ -64,7 +64,6 @@ module axi_dvi #
reg [31:0] DVI_RECT_DIR,DVI_RECT_L_W,DVI_SQU_DIR,DVI_SQU_R;
reg busy,write,R_or_W;
reg s_wready;
wire ar_enter = s_arvalid & s_arready;
wire r_retire = s_rvalid & s_rready & s_rlast;
@@ -126,8 +125,6 @@ module axi_dvi #
else if(w_enter & s_wlast) s_wready <= 1'b0;
reg [31:0] s_rdata;
reg s_rvalid,s_rlast;
wire [31:0] rdata_d = buf_addr[15:0] == 16'h0 ? DVI_RECT_DIR :
buf_addr[15:0] == 16'h4 ? DVI_RECT_L_W :
buf_addr[15:0] == 16'h8 ? DVI_SQU_DIR :
@@ -152,7 +149,6 @@ module axi_dvi #
end
end
reg s_bvalid;
always@(posedge aclk) begin
if(~aresetn) s_bvalid <= 1'b0;
else if(w_enter) s_bvalid <= 1'b1;