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FallenSigh f8edd878d4 Rewrite matmul_test for CIC-IEC Stage 3 evaluation ...

- 5000 groups (N_GROUPS=5000), group 0 all-zero as required
- MATMUL_START before computation, MATMUL_DONE after CRC
- IEEE CRC32 over 960000-byte result region (little-endian words)
- MATMUL_CRC32=XXXXXXXX format, 8 hex digits, no 0x prefix
- Uncached ExtRAM access (0xA0000000 segment)
- Removed all debug output for minimal UART traffic

2026-06-24 16:42:08 +08:00

doc

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

fpga

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

rtl

matmul_test: rewrite for ExtRAM flow, add IP error debug

2026-06-24 01:49:02 +08:00

sdk

Rewrite matmul_test for CIC-IEC Stage 3 evaluation

2026-06-24 16:42:08 +08:00

sim

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

tools

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

.gitignore

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

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