This repository has been archived on 2026-08-21. You can view files and clone it. You cannot open issues or pull requests or push a commit.

FallenSigh e39a655861 Add CRC32 self-test debug output

2026-06-24 22:42:46 +08:00

doc

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

fpga

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

rtl

Revert pipeline: restore single-cycle compute

2026-06-24 22:23:53 +08:00

sdk

Add CRC32 self-test debug output

2026-06-24 22:42:46 +08:00

sim

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

tools

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

.gitignore

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

Description

No description provided

193 MiB

Languages

Verilog 46.5%

C 27.8%

Assembly 20.5%

SystemVerilog 3.3%

Python 0.7%

Other 1.2%