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FallenSigh aaefb04737 Sync asm/ (user-sample.c + Makefile) from test branch ...

MATMUL_GROUP_NUM defaults to 5000, overridable for fast local testing.

2026-06-24 17:01:45 +08:00

doc

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

fpga

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

rtl

matmul_test: rewrite for ExtRAM flow, add IP error debug

2026-06-24 01:49:02 +08:00

sdk

Sync asm/ (user-sample.c + Makefile) from test branch

2026-06-24 17:01:45 +08:00

sim

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

tools

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

.gitignore

Track .xci/.xcix/.xdc as source files; drop Vivado-generated stubs/netlists

2026-06-23 01:33:56 +08:00

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193 MiB

Languages

Verilog 46.5%

C 27.8%

Assembly 20.5%

SystemVerilog 3.3%

Python 0.7%

Other 1.2%