114 lines
2.6 KiB
C
114 lines
2.6 KiB
C
/**
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* user-sample - CICIEC 2026 Stage 3 evaluation program
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*
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* The CDMA/matmul direct sequencer reads 5000 A/B groups from ExtRAM, writes
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* the complete C result region, and accumulates the required IEEE CRC32 in
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* hardware while the C words are streamed out of matmul.
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*/
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#include <dma.h>
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#define UART_THR (*(volatile unsigned char *)0xbf000000)
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#define UART_LSR (*(volatile unsigned char *)0xbf000005)
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#define LSR_THRE 0x20
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static inline void uart_tx(unsigned char c)
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{
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while ((UART_LSR & LSR_THRE) == 0) {
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}
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UART_THR = c;
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}
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static void uart_puts(const char *s)
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{
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while (*s) {
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uart_tx((unsigned char)*s++);
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}
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}
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static void uart_put_matmul_start_fifo(void)
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{
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UART_THR = 'M';
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UART_THR = 'A';
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UART_THR = 'T';
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UART_THR = 'M';
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UART_THR = 'U';
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UART_THR = 'L';
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UART_THR = '_';
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UART_THR = 'S';
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UART_THR = 'T';
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UART_THR = 'A';
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UART_THR = 'R';
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UART_THR = 'T';
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UART_THR = '\n';
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}
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static void uart_puthex(unsigned int val)
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{
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int i;
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for (i = 28; i >= 0; i -= 4) {
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unsigned char nibble = (unsigned char)((val >> i) & 0xf);
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uart_tx((unsigned char)(nibble < 10 ? ('0' + nibble) : ('a' + nibble - 10)));
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}
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}
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#ifndef MATMUL_GROUP_NUM
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#define MATMUL_GROUP_NUM 5000
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#endif
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#ifndef MATMUL_WRITEBACK_RESULTS
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#define MATMUL_WRITEBACK_RESULTS 1
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#endif
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#if MATMUL_FAST_START == 0
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unsigned long UART_BASE = 0xbf000000;
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#endif
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#define EXTRAM_BASE_PHYS 0x1c400000u
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#define SRC_BASE_WORDS 0u
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#define DST_BASE_WORDS (SRC_BASE_WORDS + MATMUL_GROUP_NUM * 32u)
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#define EXTRAM_PHYS_AB(g) (EXTRAM_BASE_PHYS + (SRC_BASE_WORDS * 4u) + (unsigned int)(g) * 128u)
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#define EXTRAM_PHYS_C(g) (EXTRAM_BASE_PHYS + (DST_BASE_WORDS * 4u) + (unsigned int)(g) * 192u)
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#define MATMUL_BASE_UNCACHED 0xbf500000u
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#define MATMUL_CRC (*(volatile unsigned int *)(MATMUL_BASE_UNCACHED + 0x010u))
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int main(void)
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{
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unsigned int crc;
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unsigned int seq_ctrl;
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if (MATMUL_GROUP_NUM <= 0) {
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return 0;
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}
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DMA_SEQ->STATUS = SEQ_DONE_BIT;
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DMA_SEQ->SRC_BASE = EXTRAM_PHYS_AB(0);
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DMA_SEQ->DST_BASE = EXTRAM_PHYS_C(0);
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DMA_SEQ->GROUPS = MATMUL_GROUP_NUM;
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DMA_SEQ->MAT_BASE = 0x1f500000u;
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DMA_SEQ->SRC_STRIDE = 128u;
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DMA_SEQ->DST_STRIDE = 192u;
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seq_ctrl = SEQ_START_BIT;
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#if MATMUL_WRITEBACK_RESULTS == 0
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seq_ctrl |= SEQ_SKIP_STORE_BIT;
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#endif
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uart_put_matmul_start_fifo();
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DMA_SEQ->CTRL = seq_ctrl;
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while ((DMA_SEQ->STATUS & SEQ_DONE_BIT) == 0u) {
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}
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DMA_SEQ->STATUS = SEQ_DONE_BIT;
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crc = MATMUL_CRC;
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uart_puts("MATMUL_CRC32=");
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uart_puthex(crc);
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uart_puts("\nMATMUL_DONE\n");
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return 0;
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}
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