/**
 * user-sample - CICIEC 2026 Stage 3 evaluation program
 *
 * The CDMA/matmul direct sequencer reads 5000 A/B groups from ExtRAM, writes
 * the complete C result region, and accumulates the required IEEE CRC32 in
 * hardware while the C words are streamed out of matmul.
 */

#include <dma.h>

#define UART_THR (*(volatile unsigned char *)0xbf000000)
#define UART_LSR (*(volatile unsigned char *)0xbf000005)
#define LSR_THRE  0x20

static inline void uart_tx(unsigned char c)
{
    while ((UART_LSR & LSR_THRE) == 0) {
    }
    UART_THR = c;
}

static void uart_puts(const char *s)
{
    while (*s) {
        uart_tx((unsigned char)*s++);
    }
}

static void uart_put_matmul_start_fifo(void)
{
    UART_THR = 'M';
    UART_THR = 'A';
    UART_THR = 'T';
    UART_THR = 'M';
    UART_THR = 'U';
    UART_THR = 'L';
    UART_THR = '_';
    UART_THR = 'S';
    UART_THR = 'T';
    UART_THR = 'A';
    UART_THR = 'R';
    UART_THR = 'T';
    UART_THR = '\n';
}

static void uart_puthex(unsigned int val)
{
    int i;

    for (i = 28; i >= 0; i -= 4) {
        unsigned char nibble = (unsigned char)((val >> i) & 0xf);
        uart_tx((unsigned char)(nibble < 10 ? ('0' + nibble) : ('a' + nibble - 10)));
    }
}

#ifndef MATMUL_GROUP_NUM
#define MATMUL_GROUP_NUM 5000
#endif

#ifndef MATMUL_WRITEBACK_RESULTS
#define MATMUL_WRITEBACK_RESULTS 1
#endif

#if MATMUL_FAST_START == 0
unsigned long UART_BASE = 0xbf000000;
#endif

#define EXTRAM_BASE_PHYS  0x1c400000u
#define SRC_BASE_WORDS    0u
#define DST_BASE_WORDS    (SRC_BASE_WORDS + MATMUL_GROUP_NUM * 32u)

#define EXTRAM_PHYS_AB(g) (EXTRAM_BASE_PHYS + (SRC_BASE_WORDS * 4u) + (unsigned int)(g) * 128u)
#define EXTRAM_PHYS_C(g)  (EXTRAM_BASE_PHYS + (DST_BASE_WORDS * 4u) + (unsigned int)(g) * 192u)

#define MATMUL_BASE_UNCACHED 0xbf500000u
#define MATMUL_CRC          (*(volatile unsigned int *)(MATMUL_BASE_UNCACHED + 0x010u))

int main(void)
{
    unsigned int crc;
    unsigned int seq_ctrl;

    if (MATMUL_GROUP_NUM <= 0) {
        return 0;
    }

    DMA_SEQ->STATUS = SEQ_DONE_BIT;
    DMA_SEQ->SRC_BASE = EXTRAM_PHYS_AB(0);
    DMA_SEQ->DST_BASE = EXTRAM_PHYS_C(0);
    DMA_SEQ->GROUPS = MATMUL_GROUP_NUM;
    DMA_SEQ->MAT_BASE = 0x1f500000u;
    DMA_SEQ->SRC_STRIDE = 128u;
    DMA_SEQ->DST_STRIDE = 192u;
    seq_ctrl = SEQ_START_BIT;
#if MATMUL_WRITEBACK_RESULTS == 0
    seq_ctrl |= SEQ_SKIP_STORE_BIT;
#endif

    uart_put_matmul_start_fifo();
    DMA_SEQ->CTRL = seq_ctrl;

    while ((DMA_SEQ->STATUS & SEQ_DONE_BIT) == 0u) {
    }
    DMA_SEQ->STATUS = SEQ_DONE_BIT;

    crc = MATMUL_CRC;

    uart_puts("MATMUL_CRC32=");
    uart_puthex(crc);
    uart_puts("\nMATMUL_DONE\n");

    return 0;
}