219 lines
7.6 KiB
Verilog
219 lines
7.6 KiB
Verilog
// Lightweight AXI4 register endpoint for a pseudo-random generator.
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//
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// Register map, byte offsets within the shared accelerator window:
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// 0xd000 CTRL W bit0=mix software seed, bit1=clear counters
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// 0xd004 STATUS R bit0=ready
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// 0xd008 DATA R next 32-bit random word
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// 0xd00c COUNT R number of DATA reads
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// 0xd010 SEED W software seed/mix value
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//
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// This block is deterministic unless software mixes in an external seed. It
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// intentionally uses only flops, XORs, shifts, and adders.
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module prng_axi_slave (
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input clk,
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input resetn,
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input [4:0] s_axi_awid,
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input [31:0] s_axi_awaddr,
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input [7:0] s_axi_awlen,
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input [2:0] s_axi_awsize,
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input [1:0] s_axi_awburst,
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input s_axi_awlock,
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input [3:0] s_axi_awcache,
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input [2:0] s_axi_awprot,
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input s_axi_awvalid,
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output s_axi_awready,
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input [4:0] s_axi_wid,
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input [31:0] s_axi_wdata,
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input [3:0] s_axi_wstrb,
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input s_axi_wlast,
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input s_axi_wvalid,
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output s_axi_wready,
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output [4:0] s_axi_bid,
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output [1:0] s_axi_bresp,
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output reg s_axi_bvalid,
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input s_axi_bready,
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input [4:0] s_axi_arid,
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input [31:0] s_axi_araddr,
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input [7:0] s_axi_arlen,
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input [2:0] s_axi_arsize,
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input [1:0] s_axi_arburst,
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input s_axi_arlock,
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input [3:0] s_axi_arcache,
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input [2:0] s_axi_arprot,
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input s_axi_arvalid,
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output s_axi_arready,
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output reg [4:0] s_axi_rid,
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output reg [31:0] s_axi_rdata,
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output [1:0] s_axi_rresp,
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output reg s_axi_rlast,
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output reg s_axi_rvalid,
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input s_axi_rready
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);
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localparam ADDR_CTRL = 12'h000;
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localparam ADDR_STATUS = 12'h004;
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localparam ADDR_DATA = 12'h008;
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localparam ADDR_COUNT = 12'h00c;
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localparam ADDR_SEED = 12'h010;
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assign s_axi_bresp = 2'b00;
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assign s_axi_rresp = 2'b00;
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reg [4:0] awid_reg;
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reg [31:0] awaddr_reg;
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reg [7:0] awleft_reg;
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reg write_active;
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assign s_axi_awready = !write_active && !s_axi_bvalid;
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assign s_axi_wready = write_active && !s_axi_bvalid;
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assign s_axi_bid = awid_reg;
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reg [31:0] araddr_reg;
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reg [7:0] arleft_reg;
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reg read_active;
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assign s_axi_arready = !read_active && !s_axi_rvalid;
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reg [127:0] rng_state;
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reg [63:0] free_counter;
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reg [31:0] seed_mix;
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reg [31:0] data_reads;
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wire lfsr_fb = rng_state[127] ^ rng_state[125] ^ rng_state[100] ^
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rng_state[98] ^ rng_state[27] ^ rng_state[0] ^
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free_counter[0];
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wire [127:0] rng_next = {rng_state[126:0], lfsr_fb} ^
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{free_counter, free_counter ^ {32'h0, seed_mix}};
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wire [31:0] rng_word = rng_state[31:0] ^ rng_state[63:32] ^
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rng_state[95:64] ^ rng_state[127:96] ^
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free_counter[31:0] ^ free_counter[63:32] ^
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seed_mix;
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function [31:0] apply_wstrb;
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input [31:0] old_value;
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input [31:0] new_value;
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input [3:0] strobe;
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begin
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apply_wstrb = old_value;
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if (strobe[0]) apply_wstrb[7:0] = new_value[7:0];
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if (strobe[1]) apply_wstrb[15:8] = new_value[15:8];
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if (strobe[2]) apply_wstrb[23:16] = new_value[23:16];
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if (strobe[3]) apply_wstrb[31:24] = new_value[31:24];
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end
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endfunction
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function [31:0] read_reg;
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input [31:0] addr;
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begin
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case (addr[11:0])
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ADDR_STATUS: read_reg = 32'h00000001;
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ADDR_DATA: read_reg = rng_word;
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ADDR_COUNT: read_reg = data_reads;
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ADDR_SEED: read_reg = seed_mix;
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default: read_reg = 32'h00000000;
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endcase
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end
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endfunction
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wire write_fire = s_axi_wvalid && s_axi_wready;
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wire read_fire = s_axi_rvalid && s_axi_rready;
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wire data_read_fire = read_fire && (araddr_reg[11:0] == ADDR_DATA);
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wire [31:0] next_araddr = araddr_reg + 32'd4;
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wire [31:0] next_awaddr = awaddr_reg + 32'd4;
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always @(posedge clk or negedge resetn) begin
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if (!resetn) begin
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awid_reg <= 5'b0;
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awaddr_reg <= 32'b0;
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awleft_reg <= 8'b0;
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write_active <= 1'b0;
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s_axi_bvalid <= 1'b0;
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araddr_reg <= 32'b0;
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arleft_reg <= 8'b0;
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read_active <= 1'b0;
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s_axi_rid <= 5'b0;
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s_axi_rdata <= 32'b0;
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s_axi_rlast <= 1'b0;
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s_axi_rvalid <= 1'b0;
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rng_state <= 128'h6d5a_56c3_9e37_79b9_a5a5_3c3c_c001_c0de;
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free_counter <= 64'h1;
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seed_mix <= 32'h31415927;
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data_reads <= 32'b0;
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end else begin
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free_counter <= free_counter + 64'h9e37_79b9_7f4a_7c15;
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rng_state <= rng_next;
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if (s_axi_awvalid && s_axi_awready) begin
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awid_reg <= s_axi_awid;
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awaddr_reg <= s_axi_awaddr;
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awleft_reg <= s_axi_awlen;
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write_active <= 1'b1;
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end
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if (write_fire) begin
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case (awaddr_reg[11:0])
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ADDR_CTRL: begin
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if (s_axi_wdata[0]) begin
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seed_mix <= seed_mix ^ s_axi_wdata ^ free_counter[31:0];
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rng_state <= rng_next ^ {4{s_axi_wdata}};
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end
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if (s_axi_wdata[1])
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data_reads <= 32'b0;
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end
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ADDR_SEED: begin
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seed_mix <= apply_wstrb(seed_mix, s_axi_wdata, s_axi_wstrb);
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rng_state <= rng_next ^ {s_axi_wdata, free_counter, ~s_axi_wdata};
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end
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default: begin
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end
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endcase
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if (s_axi_wlast || awleft_reg == 8'b0) begin
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write_active <= 1'b0;
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s_axi_bvalid <= 1'b1;
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end else begin
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awleft_reg <= awleft_reg - 8'd1;
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awaddr_reg <= next_awaddr;
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end
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end
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if (s_axi_bvalid && s_axi_bready)
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s_axi_bvalid <= 1'b0;
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if (s_axi_arvalid && s_axi_arready) begin
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read_active <= 1'b1;
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araddr_reg <= s_axi_araddr;
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arleft_reg <= s_axi_arlen;
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s_axi_rid <= s_axi_arid;
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s_axi_rdata <= read_reg(s_axi_araddr);
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s_axi_rlast <= (s_axi_arlen == 8'b0);
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s_axi_rvalid <= 1'b1;
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end else if (read_fire) begin
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if (data_read_fire) begin
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data_reads <= data_reads + 32'd1;
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rng_state <= rng_next ^ {rng_word, rng_word ^ free_counter[31:0],
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free_counter[63:32], ~rng_word};
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end
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if (s_axi_rlast) begin
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read_active <= 1'b0;
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s_axi_rvalid <= 1'b0;
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end else begin
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araddr_reg <= next_araddr;
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arleft_reg <= arleft_reg - 8'd1;
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s_axi_rdata <= read_reg(next_araddr);
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s_axi_rlast <= (arleft_reg == 8'd1);
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end
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end
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end
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end
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endmodule
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