61 lines
2.0 KiB
Verilog
61 lines
2.0 KiB
Verilog
module int_ctrl (
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input wire clk,
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input wire resetn,
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input wire [31:0] int_en,
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input wire [31:0] int_edge,
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input wire [31:0] int_pol,
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input wire [31:0] int_in,
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input wire [31:0] int_clr,
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input wire [31:0] int_set,
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output wire [31:0] int_out
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);
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// 同步异步输入信号，防止亚稳态
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reg [31:0] int_in_sync_d1;
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reg [31:0] int_in_sync_d2;
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reg [31:0] int_in_sync_d3; // 用于边沿检测
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always @(posedge clk or negedge resetn) begin
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if (!resetn) begin
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int_in_sync_d1 <= 32'b0;
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int_in_sync_d2 <= 32'b0;
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int_in_sync_d3 <= 32'b0;
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end else begin
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int_in_sync_d1 <= int_in;
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int_in_sync_d2 <= int_in_sync_d1;
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int_in_sync_d3 <= int_in_sync_d2;
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end
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end
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// 生成同步后的边沿信号
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wire [31:0] rising_edge = int_in_sync_d2 & ~int_in_sync_d3;
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wire [31:0] falling_edge = ~int_in_sync_d2 & int_in_sync_d3;
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// 边沿触发状态寄存器
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reg [31:0] edge_int_state;
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integer i;
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always @(posedge clk or negedge resetn) begin
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if (!resetn) begin
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edge_int_state <= 32'b0;
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end else begin
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for (i = 0; i < 32; i = i + 1) begin
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// 硬件检测优先级通常建议高于软件清除，防止丢失极窄脉冲
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if (int_edge[i]) begin
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if ((int_pol[i] && rising_edge[i]) || (!int_pol[i] && falling_edge[i]))
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edge_int_state[i] <= 1'b1;
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else if (int_set[i])
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edge_int_state[i] <= 1'b1;
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else if (int_clr[i])
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edge_int_state[i] <= 1'b0;
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end
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end
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end
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end
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// 电平触发逻辑
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wire [31:0] level_int_state = int_in_sync_d2 ^ ~int_pol;
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// 最终输出
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assign int_out = int_en & ((int_edge & edge_int_state) | (~int_edge & level_int_state));
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endmodule |