58 lines
1.6 KiB
Verilog
58 lines
1.6 KiB
Verilog
module perf_counter (
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input clk ,
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input reset ,
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input dcache_miss ,
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input icache_miss ,
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input commit_inst ,
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input br_inst ,
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input mem_inst ,
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input br_pre ,
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input br_pre_error
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);
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reg[31:0] dcache_miss_counter;
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reg[31:0] icache_miss_counter;
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reg[31:0] commit_inst_counter;
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reg[31:0] br_inst_counter;
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reg[31:0] mem_inst_counter;
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reg[31:0] br_pre_counter;
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reg[31:0] br_pre_error_counter;
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always @(posedge clk) begin
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if (reset) begin
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dcache_miss_counter <= 32'b0;
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icache_miss_counter <= 32'b0;
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commit_inst_counter <= 32'b0;
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br_inst_counter <= 32'b0;
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mem_inst_counter <= 32'b0;
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br_pre_counter <= 32'b0;
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br_pre_error_counter <= 32'b0;
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end
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else begin
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if (dcache_miss) begin
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dcache_miss_counter <= dcache_miss_counter + 32'b1;
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end
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if (icache_miss) begin
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icache_miss_counter <= icache_miss_counter + 32'b1;
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end
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if (commit_inst) begin
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commit_inst_counter <= commit_inst_counter + 32'b1;
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end
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if (br_inst) begin
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br_inst_counter <= br_inst_counter + 32'b1;
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end
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if (mem_inst) begin
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mem_inst_counter <= mem_inst_counter + 32'b1;
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end
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if (br_pre) begin
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br_pre_counter <= br_pre_counter + 32'b1;
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end
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if (br_pre_error) begin
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br_pre_error_counter <= br_pre_error_counter + 32'b1;
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end
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end
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end
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endmodule
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