FallenSigh
4538ec496f
At mlkem_clk=100 MHz the worst path (WNS -2.14 ns) was coeff_bram read -> butterfly diff (b-a) -> barrett first multiply stage, all in one cycle. The butterfly took its operands combinationally from the BRAM read (unlike poly_mul's basecase, which already registers them). Add an input register stage (a/b/zeta/mode/valid) in butterfly_unit_pipe so the BRAM read and the first multiply land in separate cycles; feed the a/b/mode alignment delay lines from the registered inputs. Butterfly latency 8->9; ntt_core writeback address delay lines deepened 9->10 to match. Verified byte-exact vs NIST KAT: NTT standalone TB 19/19 (fwd+inv), Encaps 9/9, Decaps 9/9, hello_world e2e — all PASS. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>