218 lines
9.0 KiB
C
218 lines
9.0 KiB
C
/**
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* user-sample - CIC-IEC 2026 Stage 3 Evaluation Program
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*
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* (ULTIMATE PERFORMANCE DMA + PING-PONG BUFFER ARCHITECTURE v2)
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*
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* Optimizations over v1:
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* 1. Pre-fire DMA Ch0 load at loop tail → fully overlaps with IP compute
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* 2. Inlined wait loops → zero function-call overhead in hot path
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* 3. Inlined DMA start → skips redundant STATUS_BUSY_BIT check
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* 4. XOR bank toggle → avoids g%2 recomputation per iteration
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*/
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#include <dma.h>
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/* ─── UART 16550 direct access (bypasses slow printf/picolibc) ──────── */
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#define UART_THR (*(volatile unsigned char *)0xbf000000)
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#define UART_LSR (*(volatile unsigned char *)0xbf000005)
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#define LSR_THRE 0x20
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static inline void uart_tx(unsigned char c) {
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while (!(UART_LSR & LSR_THRE)) {}
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UART_THR = c;
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}
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static void uart_puts(const char *s) {
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while (*s) uart_tx(*s++);
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}
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static void uart_puthex(unsigned int val) {
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int i;
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for (i = 28; i >= 0; i -= 4) {
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unsigned char nibble = (val >> i) & 0xF;
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uart_tx(nibble < 10 ? '0' + nibble : 'a' + nibble - 10);
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}
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}
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/* ─── Configurable group count (default 5000) ──────────────────────── */
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#ifndef MATMUL_GROUP_NUM
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#define MATMUL_GROUP_NUM 5000
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#endif
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/* ─── BSP globals ─────────────────────────────────────────────────── */
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unsigned long UART_BASE = 0xbf000000;
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unsigned long CONFREG_TIMER_BASE = 0xbf20f100;
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unsigned long CONFREG_CLOCKS_PER_SEC = 50000000L;
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unsigned long CORE_CLOCKS_PER_SEC = 33000000L;
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/* ─── Memory layout ────────────────────────────────────────────────── */
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#define EXTRAM_BASE_PHYS 0x1c400000
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#define EXTRAM_BASE_UNCACHED (0xA0000000 | (EXTRAM_BASE_PHYS & 0x1FFFFFFF))
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#define SRC_BASE_WORDS 0
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#define DST_BASE_WORDS (SRC_BASE_WORDS + MATMUL_GROUP_NUM * 32)
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#define RESULT_WORDS (MATMUL_GROUP_NUM * 48)
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/* ExtRAM Physical Addresses for DMA */
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#define EXTRAM_PHYS_AB(g) (EXTRAM_BASE_PHYS + (SRC_BASE_WORDS * 4) + (g) * 128)
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#define EXTRAM_PHYS_C(g) (EXTRAM_BASE_PHYS + (DST_BASE_WORDS * 4) + (g) * 192)
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/* ─── MATMUL IP registers (Ping-Pong Memory Map) ──────────────────── */
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#define MATMUL_BASE_PHYS 0x1f500000
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#define MATMUL_BASE_UNCACHED 0xbf500000
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#define MATMUL_CTRL (MATMUL_BASE_UNCACHED + 0x000)
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#define MATMUL_STATUS (MATMUL_BASE_UNCACHED + 0x004)
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#define CTRL_START_B0 0x1
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#define CTRL_START_B1 0x2
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#define STATUS_DONE 0x2
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#define STATUS_ERROR 0x4
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#define MATMUL_CRC (MATMUL_BASE_UNCACHED + 0x010)
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/* ─── Pre-computed DMA burst control word ──────────────────────────── */
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#define DMA_CTRL_VAL (CTRL_BURST_SIZE(2) | CTRL_BURST_LEN(63) | CTRL_START_BIT)
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#define MATMUL_EP_ID 0
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/* ═══════════════════════════════════════════════════════════════════ */
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int main(void)
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{
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if (MATMUL_GROUP_NUM <= 0) return 0;
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/* ── Hot-path local volatile pointers (one-time addr calc) ──────── */
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volatile unsigned int *mat_status = (volatile unsigned int *)MATMUL_STATUS;
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volatile unsigned int *mat_ctrl = (volatile unsigned int *)MATMUL_CTRL;
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volatile unsigned int *mat_crc = (volatile unsigned int *)MATMUL_CRC;
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volatile dma_ch_regs_t *ch0 = DMA_CH(0);
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volatile dma_ch_regs_t *ch1 = DMA_CH(1);
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unsigned int crc;
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int g, bank;
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unsigned int ctrl_start[2] = {CTRL_START_B0, CTRL_START_B1};
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/* ── Start marker (must be first output) ──────────────────── */
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uart_puts("MATMUL_START\r\n");
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// Reset IP state
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*mat_status = STATUS_DONE | STATUS_ERROR;
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*mat_crc = 0;
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/* ═══════════════════════════════════════════════════════════════
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* PROLOGUE: Load group 0 → Bank 0, start IP, pre-fire group 1
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* ═══════════════════════════════════════════════════════════════ */
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// DMA Ch0: Load group 0 A+B (128 bytes) → IP Bank 0
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ch0->SRC_ADDR = EXTRAM_PHYS_AB(0);
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ch0->DST_ADDR = 0;
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ch0->LENGTH = 128;
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ch0->MODE = DMA_MODE_MEM2EP;
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ch0->EP_CFG = DMA_EP_CFG(MATMUL_EP_ID, 0, 0);
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ch0->CTRL = DMA_CTRL_VAL;
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while (!(ch0->STATUS & STATUS_DONE_BIT)) {}
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ch0->STATUS = STATUS_DONE_BIT;
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// Start IP Bank 0 (group 0)
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*mat_ctrl = ctrl_start[0];
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// Pre-fire: DMA Ch0 load group 1 → Bank 1 (overlaps with IP compute)
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if (MATMUL_GROUP_NUM > 1) {
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ch0->SRC_ADDR = EXTRAM_PHYS_AB(1);
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ch0->DST_ADDR = 0;
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ch0->LENGTH = 128;
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ch0->MODE = DMA_MODE_MEM2EP;
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ch0->EP_CFG = DMA_EP_CFG(MATMUL_EP_ID, 1, 0);
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ch0->CTRL = DMA_CTRL_VAL;
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}
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/* ═══════════════════════════════════════════════════════════════
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* MAIN LOOP: Fully-pipelined — pre-fire DMA load at loop tail
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*
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* At iteration g:
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* IP is computing group (g-1) on prev_bank
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* Ch0 loaded group g to cur_bank (pre-fired in iteration g-1)
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*
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* Pipeline:
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* Ch0: | load g+1 | | load g+2 |
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* Ch1: | store g-1 | | store g |
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* IP : | compute g | | compute g+1 |
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* ═══════════════════════════════════════════════════════════════ */
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bank = 1; // cur_bank for iteration g=1; prev_bank = bank ^ 1
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for (g = 1; g < MATMUL_GROUP_NUM; g++) {
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int cur_bank = bank;
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int prev_bank = bank ^ 1;
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// 1. Wait for previous IP computation (group g-1 on prev_bank)
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while (!(*mat_status & STATUS_DONE)) {}
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*mat_status = STATUS_DONE;
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// 2. Ensure previous DMA Ch1 store is done (group g-2)
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if (g > 1) {
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while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
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ch1->STATUS = STATUS_DONE_BIT;
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}
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// 3. Start DMA Ch1 store: group (g-1) result → ExtRAM
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ch1->SRC_ADDR = 0;
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ch1->DST_ADDR = EXTRAM_PHYS_C(g - 1);
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ch1->LENGTH = 192;
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ch1->MODE = DMA_MODE_EP2MEM;
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ch1->EP_CFG = DMA_EP_CFG(MATMUL_EP_ID, prev_bank, 0);
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ch1->CTRL = DMA_CTRL_VAL;
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// 4. Wait for current DMA Ch0 load (group g → cur_bank, pre-fired in iteration g-1)
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while (!(ch0->STATUS & STATUS_DONE_BIT)) {}
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ch0->STATUS = STATUS_DONE_BIT;
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// 5. Start IP computation for current group on cur_bank
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*mat_ctrl = ctrl_start[cur_bank];
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// ★ 6. PRE-FIRE: DMA Ch0 load next group (g+1) → next_bank
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// This runs CONCURRENTLY with IP computation started in step 5!
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if (g < MATMUL_GROUP_NUM - 1) {
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int next_bank = bank ^ 1;
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ch0->SRC_ADDR = EXTRAM_PHYS_AB(g + 1);
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ch0->DST_ADDR = 0;
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ch0->LENGTH = 128;
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ch0->MODE = DMA_MODE_MEM2EP;
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ch0->EP_CFG = DMA_EP_CFG(MATMUL_EP_ID, next_bank, 0);
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ch0->CTRL = DMA_CTRL_VAL;
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}
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// Toggle bank for next iteration
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bank ^= 1;
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}
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/* ═══════════════════════════════════════════════════════════════
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* EPILOGUE: Flush the final group
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* ═══════════════════════════════════════════════════════════════ */
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// Wait for last IP computation
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while (!(*mat_status & STATUS_DONE)) {}
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*mat_status = STATUS_DONE;
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// Wait for previous DMA store and start/complete final store
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while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
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ch1->STATUS = STATUS_DONE_BIT;
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ch1->SRC_ADDR = 0;
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ch1->DST_ADDR = EXTRAM_PHYS_C(MATMUL_GROUP_NUM - 1);
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ch1->LENGTH = 192;
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ch1->MODE = DMA_MODE_EP2MEM;
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ch1->EP_CFG = DMA_EP_CFG(MATMUL_EP_ID, (MATMUL_GROUP_NUM - 1) % 2, 0);
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ch1->CTRL = DMA_CTRL_VAL;
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while (!(ch1->STATUS & STATUS_DONE_BIT)) {}
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ch1->STATUS = STATUS_DONE_BIT;
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/* ── Read hardware CRC32 ──────────────────────────────────── */
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crc = *mat_crc;
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uart_puts("MATMUL_CRC32=");
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uart_puthex(crc);
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uart_puts("\r\nMATMUL_DONE\r\n");
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return 0;
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}
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